Divide by three clock divider with symmertical output

Details Divide by three clock divider with symmertical output Divide by three clock divider with symmertical output

1980-09-25

1982-09-07

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307225R, H03K 2100

Patent

active

043486401

ABSTRACT:
A digital circuit receives symmetrical clock pulses of frequency F and outputs symmetrical pulses of frequency 1/3 F. A divide by one and one-half circuit clocks a divide by two flip-flop resulting in a symmetrical divide by three output. The divide by one and one-half circuit includes a pair of JK flip-flops and logic gates which receive clock pulses of frequency F and generate a plurality of staggered signal streams with nonsymmetrical pulses of frequency 1/3 F and a duty cycle of substantially 33%. The input clock pulses are gated against two of these streams to provide an output pulse during the first half of the duty portion of a cycle of one of the streams, and another output pulse during the second half of the duty portion of a cycle of the other stream, to provide an output frequency of 2/3 F which then clocks the divide by two flip-flop.

REFERENCES:
patent: 3439278 (1969-04-01), Farrow
patent: 3473129 (1969-10-01), Tschannen
patent: 3571728 (1971-03-01), Andrea et al.
patent: 3902125 (1975-08-01), Oliva
patent: 3943379 (1976-03-01), McGuffin
patent: 4041403 (1977-08-01), Chiapparoli

Affiliated with

Also associated with

Rating

Divide by three clock divider with symmertical output does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Divide by three clock divider with symmertical output, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Divide by three clock divider with symmertical output will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1344482