Divide-by-N clock divider circuit with minimal additional delay

Details Divide-by-N clock divider circuit with minimal additional delay Divide-by-N clock divider circuit with minimal additional delay

2002-08-02

2003-05-20

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C327S117000, C377S047000, C377S052000

Reexamination Certificate

active

06566918

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to clocking circuits for digital systems. More specifically, the present invention relates to a programmable divide-by-N clock divider circuit with optional duty cycle correction that adds only a minimal delay to the clock path.
BACKGROUND OF THE INVENTION
Digital circuits such as board level systems and integrated circuit (IC) devices, including programmable logic devices (PLDs), and microprocessors, use clocking signals for a variety of reasons. For example, synchronous systems use global clock signals to synchronize various circuits across the board or IC device.
However, as the complexity of digital circuits increases, clocking schemes for synchronous systems become more complicated. Many complex digital circuits such as PLDs and microprocessors use multiple clock signals at different frequencies. For example, in some PLDs, some of the programmable logic blocks can be operated at a first clock frequency while other logic blocks are operated at a second clock frequency.
Multiple clock generating circuits can be used to generate the multiple clock signals. However, clock generating circuits typically consume a large amount of device or board space. Therefore, most systems use one clock generating circuit to generate a first clock signal and a specialized circuit to derive other clock signals from the first clock signal. For example, clock dividers are often used to generate clock signals of lower frequency from an input clock signal.
FIG. 1
shows a conventional divide-by-four clock divider
100
that receives an input clock signal CKIN and generates a divide-by-two clock signal CLKD
2
and a divide-by-four clock signal CLKD
4
. (In the present specification, the same reference characters are used to refer to terminals, signal lines, and their corresponding signals.) Clock divider
100
comprises a conventional 2-bit counter
110
. Input clock signal CKIN is applied to the clock terminal of 2-bit counter
110
. Counter
110
drives clock signals CLKD
2
and CLKD
4
on output terminals
00
and
01
, respectively. Output terminals
00
and
01
provide the least significant and most significant bits of 2-bit counter
110
, respectively.
FIG. 1A
is a timing diagram for clock divider
100
of FIG.
1
. As can easily be seen from
FIG. 1A
, if input clock signal CKIN has a clock period P, then divide-by-two clock signal CLKD
2
has a clock period of 2P. Similarly, divide-by-four clock signal CLKD
4
has a period of 4P. Thus, the frequency of clock signal CLKD
2
is half the frequency of input clock signal CKIN, and the frequency of clock signal CLKD
4
is one-fourth the frequency of signal CKIN.
Some known clock dividers combine the output signals of a counter to generate other clock signals. For example,
FIG. 2
shows a known divide-by-four clock divider circuit. A timing diagram for the circuit of
FIG. 2
is shown in FIG.
2
A.
Clock divider
200
includes toggle flip-flops
201
and
202
, AND gate
203
, and OR gate
204
. AND gate
203
combines signals DIVEN (a divider enable input signal) and CKIN (the input clock signal) to provide signal CK. Input clock signal CKIN also drives clock terminal C of flip-flop
201
, while the output terminal Q of flip-flop
201
provides signal DIV
2
. Signal DIV
2
drives clock terminal C of flip-flop
202
, while the output terminal Q of flip-flop
202
provides signal DIV
4
. The reset terminals R of flip-flops
201
and
202
are driven by divider enable signal DIVEN. OR gate
204
is driven by signals CK, DIV
2
, and DIV
4
, and provides output signal CKOUT.
As shown in
FIG. 2A
, on the first CKIN clock edge after divider enable signal DIVEN goes high, signals DIV
2
and DIV
4
both go high. If the period of signal CKIN is denoted as P, then signal DIV
2
has a period of 2P, and signal DIV
4
has a period of 4P. Signal CKOUT follows signal CKIN one out of every four input clock periods. During the other three clock periods, signal CKOUT is high.
Clock divider
200
of
FIG. 2
combines the two flip-flop outputs DIV
2
and DIV
4
using a combinatorial function (OR). Essentially, the flip-flop output signals are decoded and combined with the clock input signal CKIN. This concept can be extended to create larger counters. For example, adding another flip-flop with a clock terminal C driven by signal DIV
4
and providing an output signal DIV
8
, and ORing the DIV
8
signal-with DIV
2
and DIV
4
, creates a divide-by-eight counter. Note that this type of counter is limited to divisors that are powers of two.
Note further that the delay from the input clock signal CKIN to the output clock signal CKOUT includes the combinatorial-logic (e.g., OR gate
204
) used to decode the flip-flop outputs. This delay can be significant, particularly when wider OR gates are required. Further, when the counter becomes too large, it is impractical to implement the resulting wide OR gate using CMOS logic.
Therefore, it is desirable to provide a clock divider circuit that has a fast through-delay, e.g., does not require wide combinatorial logic functions in the clock path. It is further desirable to provide a clock divider circuit that supports divisors other than the powers of two.
SUMMARY OF THE INVENTION
The invention provides a divide-by-N clock divider circuit that adds little additional delay on the clock path. N can be any integer, and the value of N does not affect the clock path delay. The divide-by-N divider circuits of the invention include a control circuit and a logical NOR circuit, where the control circuit is clocked by an input clock signal and the NOR circuit combines the input clock signal with the output signal of the control circuit. The control circuit acts as a filter, selecting pulses from the input clock signal to be passed to the output terminal. By selecting one out of every N input clock pulses, a divide-by-N clock divider is implemented. In some embodiments, the value of N is programmable. In some embodiments, optional duty cycle correction is available.
According to one embodiment of the invention, a clock divider circuit includes a control circuit and a NOR circuit. The control circuit includes N−1 (N minus one) flip-flops coupled in series, i.e., a data output terminal of each flip-flop drives a data input terminal of the next flip-flop in the series (possibly with intervening logic). An input clock signal drives the clock terminal of each flip-flop. The last flip-flop in the series drives the data input terminal of the first flip-flop in the series. The logical NOR circuit is driven by the last flip-flop and by the input clock signal, and provides the output clock signal of the clock divider circuit.
In some embodiments, a divider enable signal is provided. When the divider is disabled, the flip-flops are initialized to known values. In some of these embodiments, the flip-flops are reset flip-flops and the known values are all zero.
Some embodiments include an optional duty cycle correction feature. In one such embodiment, the clock divider circuit includes a counter circuit and a multiplexer circuit. The counter circuit provides a divide-by-M clock signal, where M is an integral multiple of two. A duty cycle correction enable signal controls the multiplexer circuit to select between the outputs of the control circuit and the counter circuit. In some embodiments, the counter circuit is a Gray code counter, i.e., the counter implements a Gray code, wherein only one bit changes in response to any given clock edge.
Some embodiments of the invention include a programmable divisor feature. One such embodiment includes a programmable control circuit and a NOR circuit. The programmable control circuit includes a plurality of flip-flops coupled in series, including a first flip-flop and a last flip-flop. An input clock signal drives the clock terminal of each flip-flop. The last flip-flop drives the data input terminal of the first flip-flop. The logical NOR circuit is driven by the last flip-flop and by the input clock signal, and provides the output clock signal of the clock div

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