Diversity-mode delay lock loop circuit and associated method...

Pulse or digital communications – Receivers – Interference or noise reduction

Reexamination Certificate

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Reexamination Certificate

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07369632

ABSTRACT:
A receiver and method are provided for receiving signals transmitted thereto from a transmitter during operation of a radio communication system. To synchronize the receiver with the transmitter, the receiver includes a delay lock loop circuit capable of receiving a pilot signal and a diversity signal transmitted from a plurality of transmit antennas and/or received by a plurality of receive antennas. The delay lock loop circuit is capable of calculating a first error signal based upon the pilot signal, and a second error signal based upon the diversity signal. The delay lock loop circuit is then capable of forming a combined error signal based upon the first and second error signals, and capable of synchronizing the receiver with the transmitter based upon the combined error signal.

REFERENCES:
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patent: 6525615 (2003-02-01), Masenas et al.
patent: 6735242 (2004-05-01), Kenney et al.
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patent: 2003/0063657 (2003-04-01), Bultan et al.
patent: 2004/0151272 (2004-08-01), Kenney et al.
Kiasaleh, Channel-Aided, Decision-Directed Delay-Locked Loop for Pilot Symbol Aided CDMA Communications Impaired by Fast Frequency-Selective Rayleigh Fading and User Interference, 2000, IEEE, p. 1392-1407.
Oh, Coherent DLL Code Tracking and BER Effect on QPSK Demodulation in Wideband DS-CDMA Reverse Link, 1998, IEEE, p. 2408-2410.

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