Diversity circuit and frame phase (or sampling timing) estimatio

Pulse or digital communications – Spread spectrum – Direct sequence

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455135, H04B 710

Patent

active

051649640

ABSTRACT:
A diversity circuit is disclosed which includes CIR estimation circuits, error computers for computting the ratios of the estimated CIR power to the error power between the estimated and actual received signal for respective received signals, a comparator for comparing respective ratios, and a selector for outputting the received signal and the CIR corresponding to the maximum power ratio. A frame phase (or sampling timing) estimation circuit using the diversity circuit further includes a delay circuit for providing a received signal with different delays, whereby the selector outputs the delayed received signal and the CIR corresponding to the maximum power ratio.

REFERENCES:
patent: 4715048 (1987-12-01), Masamura
patent: 4935940 (1990-06-01), Reindl
patent: 4972423 (1990-11-01), Le Polozec et al.
patent: 5031193 (1991-07-01), Atkinson et al.
Aria et al., "Design & Performance of Synchronization Techniques and Viterbi, Adaptive Equalizers for Narrow Band TDMA Mobile Radio".
Kazuhiro, "A New Post-Detection Selection Diversity with MLSE Equalization", Automnal National Session of the Institute of Electronics, Information & Communication Engineer, 1989, B502, pp. 2-172.

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