Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2002-09-25
2003-12-02
Wille, Douglas A. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C365S148000
Reexamination Certificate
active
06657278
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to electronic devices and, more particularly, to memory semiconductor devices having diverse band gap energy levels providing high forward-to-reverse current ratios.
BACKGROUND OF THE INVENTION
Memory circuits are at the core of any computer system. In this regard, one of the driving forces in memory circuit design has been to place a maximum number of memory cells in as small a physical space as possible. Initially, memory circuit design was constrained by the planar nature (i.e., two-dimensional) of the physical substrates upon-which memory cells were fabricated. This constraint has given way to three-dimensional spaces that include the area provided by the physical substrates and the space above and-below such substrates. As such, memory circuit designers introduced vertical memory cells resulting in three-dimensional memory arrays.
Vertical memory cells have themselves evolved into various forms. For example, U.S. Pat. No. 6,034,882 to Johnson et al., which is hereby fully incorporated by reference, describes a vertically fabricated memory cell having a steering element for enhancing the flow of current in one direction and a state change element for retaining a programmed state. The steering element functions similar to a diode and conducts more readily in one direction than in the other. In this regard, a current can be forced into the state change element for programming or for sensing the state thereof.
Additionally, U.S. pending application Ser. No. 09/560,626, and its continuation-in-part, U.S. patent application Ser. No. 09/814,727, both assigned to the assignee of the instant application, and titled “Three-dimensional Memory Array and Method of Manufacture,” and which are both hereby also fully incorporated by reference, describe a multi-level memory array having a plurality of rail-stacks forming memory cells. As such, the various material layers of the rail-stacks are configured to perform diode functions by conducting current in one direction more readily than in the other. This function facilitates programming of the memory cells and sensing of the states thereof.
In this regard, the diode functions accomplished by the above-described memory designs are typically performed by two layers of a single semiconductor material such as, for example, silicon (Si)—but with each layer having an opposite conductivity dopant (e.g., n-type silicon and p-type silicon). Such structures have been commonly referred to a homo-structures or homo-junctions because a single semiconductor material is used. In terms of ease of fabrication, relying on a single semiconductor material such as Si, SiGe, GaAs, or InP, for accomplishing the diode functions is advantageous. However, relying on a single semiconductor material for these functions also places certain constraints on the achievable device performance. For example, physical dimensions and doping concentrations can be varied to increase device performance, but, only to a limit before other device characteristics begin to decrease or fail.
Hence, materials and methods for allowing higher achievable device performance such as, for example, the diode function of memory cells, is highly desirable.
SUMMARY OF THE INVENTION
The present invention employs hetero-structures, or hetero-junctions, having a plurality of band gap energy levels for increasing the forward-to-reverse current ratios of PN junctions. As used herein, the terms “hetero-structure” or “hetero-junction” mean a structure having at least first-type and second-type semiconductor materials either in contact with each other to form a junction or separated by an insulator. A PN junction is a junction between opposite polarity-type (i.e., P-type and N-type) doped semiconductor materials. As such, a PN junction can. be realized as a hetero-junction.
In this regard, one embodiment of the present invention is directed to a semiconductor device comprising as first semiconductor layer having a first band gap energy level, a second semiconductor layer having a second band gap energy level, and an insulating layer disposed between the first and second layers that is capable of being selectively breached by passing a current between one of the first and second semiconductor layers. The second band gap energy level is different from the first band gap energy level. As will be described in more detail below, a band gap energy level is different from one or more other band gap energy levels when it is not the same or not equal to the other band gap energy level(s). This includes a particular band gap energy level being greater or less than one or more other band gap energy levels. So formed, the wide band gap energy level differences provide a higher ratio of forward-to-reverse current between the first and second semiconductor layers when such layers form a PN junction.
Therefore, it is an advantage of the present invention to provide a hetero-structure for use in memory devices.
It is yet another advantage of the present invention to provide a hetero-structure having a wide band gap energy level difference for increasing the forward-to-reverse current ratio of diode functions of memory devices.
It is still further an advantage of the present invention to provide a hetero-structure that utilizes existing semiconductor fabrication technology.
REFERENCES:
patent: 5360986 (1994-11-01), Candelaria
patent: 5745407 (1998-04-01), Levy et al.
patent: 6034882 (2000-03-01), Johnson et al.
patent: 6185122 (2001-02-01), Johnson et al.
patent: 6420215 (2002-07-01), Knall et al.
patent: 6549447 (2003-04-01), Fricke et al.
patent: 10079521 (1998-03-01), None
5.1.4 Wavelength Engineering (5 pages).
Calfee Halter & Griswold
Matrix Semiconductor Inc.
Pejic Nenad
Toth Liza K.
Wille Douglas A.
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