Coded data generation or conversion – Analog to or from digital conversion – Increasing converter resolution
Reexamination Certificate
2001-02-05
2002-05-14
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Increasing converter resolution
C341S139000
Reexamination Certificate
active
06388595
ABSTRACT:
BACKGROUND OF THE INVENTION
In digital oscilloscopes, analog signals are sampled at discrete time intervals. An Analog-to-Digital Converter (A/D) converts the sampled signal to a digital representation. The digital representation is usually stored in memory. In many cases it is desirable to store the data at less frequent time intervals than it is sampled by the A/D converter. This is known as subsampling the data. Subsampling can lead to aliasing in the stored data. That is, if the analog signal contains frequencies higher than ½ the subsampling frequency, these higher frequencies will show up in the stored data as a lower frequency signal. This problem is known as aliasing. Aliasing can lead to the display of faulty data on oscilloscopes. For example, a 99 MHz sine wave subsampled at a ten nanosecond (10 ns) interval will appear on screen as a 1 MHz sine wave.
There have been many attempts to solve the aliasing problem. Prior art U.S. patent U.S. Pat. No. 5,115,189 (Holcomb) entitled, ANTI-ALIASING DITHERING METHOD AND APPARATUS FOR LOW FREQUENCY SIGNAL SAMPLING, addressed the problem in a manner that is feasible only for low sampling rates. In Holcomb, data was processed one sample at a time as it was sampled by the A/D converter. Cost effective circuitry can not process data in this manner at high sampling rates. At lower sampling rates the dither is effective only for lower input signal frequencies. Also at lower sampling frequencies the aliased signals are not converted to noise as effectively. The bandwidth of the noise is lower causing aliasing artifacts to be more prevalent.
U.S. Pat. No. 5,789,954 (Toeppen, et al.) entitled PHASE DITHER OF AN ACQUISITION CLOCK USING A DELAY LOCK LOOP, modulates the phase of an acquisition clock by summing an offset voltage with the output of the phase detector of a delay loop. The offset voltage is generated by a digital to analog (D/A) converter which receives input values from a microprocessor which is running a pseudo-random number generator routine. The solution of Toeppen is suitable for relatively low speed operation only due to the long settling time required for the loop to lock between acquisitions.
What is needed is an apparatus that solves the aliasing problem at the high speeds required of today's oscilloscopes.
SUMMARY OF THE INVENTION
The subject invention addresses the problem of aliasing in subsampled data by adding dither to the timing of the subsampling of the data. The subject invention solves the speed problem referred-to above by dithering data that has been demultiplexed into a wider and slower stream of samples. It is herein recognized that to maintain a high acquisition rate one should randomly select samples after demultiplexing rather than attempting to modify the A/D converter sampling clock.
REFERENCES:
patent: 3562420 (1971-02-01), Thompson
patent: 4142146 (1979-02-01), Schumann
patent: 4700173 (1987-10-01), Araki et al.
patent: 4901265 (1990-02-01), Kerr et al.
patent: 5115189 (1992-05-01), Holcomb
patent: 5530442 (1996-06-01), Norsworthy et al.
patent: 5789954 (1998-08-01), Toeppen
Edwards Forrest A.
Etheridge Eric P.
Lenihan Thomas F.
Tektronix Inc.
Wamsley Patrick
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