Dither error correction

Details Dither error correction Dither error correction

1992-04-16

1993-02-23

Logan, Sharon D.

Coded data generation or conversion

Analog to or from digital conversion

Increasing converter resolution

341118, 341155, H03M 120

Patent

active

051894181

ABSTRACT:
A technique for correcting settling, feedthru, and higher order error mechanisms in a dithered analog-to-digital conversion circuit is disclosed. For each conversion cycle of an ADC, a dither signal is generated by converting a current dither value from a sequence of dither values and is then added to an analog input signal. The analog input signal and dither signal are converted by the ADC, and the current dither value subtracted, to form a digital output signal. Correction signals proportional to dither values which precede or follow the current dither value in the sequence are also generated each conversion cycle and subtracted from the analog input signal. The proportions used to produce the correction signals are adjusted dynamically according to the amount of correlation between the digital output signal and the dither values used to form the correction signals. The correction signals are thereby made to equal the amount of error contributed by a corresponding one of the error mechanisms.

REFERENCES:
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patent: 4761634 (1988-08-01), Yamaguchi et al.
patent: 4814767 (1989-03-01), Fernandes et al.
patent: 4963881 (1990-10-01), Franceshini
patent: 4994803 (1991-02-01), Blackham
patent: 5134399 (1992-07-01), Hiller
Honig, et al., Adaptive Filters, Excerpt from book, Sections 3.1 and 3.2, pp. 48-53, 1985.

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