Distribution charge pump for nonvolatile memory device

Details Distribution charge pump for nonvolatile memory device Distribution charge pump for nonvolatile memory device

1996-10-31

1998-06-16

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Signal transmission integrity or spurious noise override

327536, H03K 1716

Patent

active

057677298

ABSTRACT:
A distribution charge pump is disclosed that provides a high voltage output that can be used to write or erase EEPROM cells. The charge pump is enabled by a high (VCC) input signal, which is input to a pair of always-on pass transistors. The output of one of these pass transistors turns on a third transistor whose source is tied to an internal node that is coupled to one terminal of a MOS capacitor and the gate of a fourth transistor. The other terminal of the MOS capacitor is tied to a clock signal and the source and drain of the fourth transistor are tied respectively to the charge pump output and a high voltage power supply node (VPP). The capacitor stores charge on the internal node when the clock signal goes high and discharges when the clock signal goes low. Due to this discharge, the voltage at the internal node drops, which causes the third transistor to turn on and supply charge to the internal node, preventing the complete discharge of charges stored during the positive phase of the clock cycle. Therefore, the voltage at the first node rises over subsequent clock pulses. The fourth transistor turns on whenever the voltage at the first node is above threshold; thus the pump output tracks the voltage on the internal node. Because the drain of the second pump transistor is tied to VPP, the pump output can never rise higher than VPP, which prevents high voltage problems in the memory circuits.

REFERENCES:
patent: 5039882 (1991-08-01), Arakawa
patent: 5336952 (1994-08-01), Iwahashi et al.
patent: 5513142 (1996-04-01), Arimoto et al.
patent: 5594380 (1997-01-01), Nam
patent: 5677645 (1997-10-01), Merritt

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