Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Patent
1995-06-30
1997-01-28
Nguyen, Viet Q.
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
36518905, 365204, 365205, 365233, 3652335, G11C 11401
Patent
active
055983766
ABSTRACT:
An integrated circuit memory device is designed to perform high speed data write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. A transition of the Read/Write control line during a burst access is used to terminate the burst access and initialize the device for another burst access. Write cycle times are maximized to allow for increases in burst mode operating frequencies. Local logic gates near array sense amplifiers are used to control write data drivers to provide for maximum write times without crossing current during input/output line equilibration periods. By gating global write enable signals with global equilibrate signals locally at data sense amp locations, local write cycle control signals are provided which are valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory devices. For nonburst mode memory devices such as EDO and Fast Page Mode, the write function may begin immediately following the end of the equilibration cycle to provide a maximum write time without interfering with the address setup time of the next access cycle.
REFERENCES:
patent: 4344156 (1982-08-01), Eaton et al.
patent: 4484308 (1984-11-01), Lewandowski et al.
patent: 4562555 (1985-12-01), Ouchi et al.
patent: 4567579 (1986-01-01), Patel et al.
patent: 4575825 (1986-03-01), Ozaki et al.
patent: 4603403 (1986-07-01), Toda
patent: 4618947 (1986-10-01), Tran et al.
patent: 4649522 (1987-03-01), Kirsch
patent: 4685089 (1987-08-01), Patel et al.
patent: 4707811 (1987-11-01), Takemae et al.
patent: 4788667 (1988-11-01), Nakano
patent: 4875192 (1989-10-01), Matsumoto
patent: 5267200 (1993-11-01), Tobita
patent: 5268865 (1993-12-01), Takasugi
patent: 5357469 (1994-10-01), Sommer et al.
patent: 5392239 (1995-02-01), Margulis et al.
patent: 5430680 (1995-07-01), Parris
patent: 5452259 (1995-09-01), McLaury
Samsung Electronics, "Samsung Synchronous DRAM", Mar. 1993, pp. 1-16.
Oki Electric Ind Co., Ltd, "Burst DRAM Function & Pinout", 2nd presentation, Item #619, Sep. 1, 1994.
Toshiba, "Pipelined Burst DRAM", Dec. 1994, JEDEC JC-42.3 Hawaii.
Toshiba America Electronic Components, Inc., "Application Specific DRAM,, 1994", pp. C-178, C-260, C218.
Micron Semiconductor, Inc., "Synchronous DRAM 2 MEG.times.8 SDRAM", pp. 2-43 through 2-83.
Toshiba America Electronic Components, Inc., "4M DRAM 1991", pp. A-137-A-159.
Micron Semiconductor, Inc., "1994 DRAM Data Book", entire book.
Mosel-Vitelic V53C8257H DRAM Specification Sheet, 20 pgs.
Manning Troy A.
Merritt Todd A.
Micro)n Technology, Inc.
Nguyen Viet Q.
LandOfFree
Distributed write data drivers for burst access memories does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Distributed write data drivers for burst access memories, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Distributed write data drivers for burst access memories will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-945645