Excavating
Patent
1989-05-08
1992-10-06
Smith, Jerry
Excavating
371 62, G06F 1100
Patent
active
051538830
ABSTRACT:
A distributed timing signal generator as a component of a per-pin architecture tester is disclosed. Start control circuits are provided per pin, and the same start signal is provided from the outside for each of the start control circuits. Each of the start control circuits then determines the start timing for at least one timing generator accommodated therein by the variable set values, and starts to control each timing generator at the thus-determined start timing. Thus, timing signals which correspond to the respective variable set values are produced from the respective timing generators with high timing accuracy and in interlock with each other. It is possible to provide timing generators for a driver, for input/output (I/O) control, and for a comparator, and in this case it is easy to obtain the respective timing signals.
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IEEE International Test Conference 1983, "Individual Signal Path Calibration for Maximum Timing Accuracy in a High Pincount VLSI Test System", pp. 188-192.
IEEE International Test Conference 1983, "Optimizing the Timing Architecture of a Digital LSI Test System", pp. 200-209.
Hayashi Yoshihiko
Suga Takashi
Chung Phung M.
Hitachi , Ltd.
Smith Jerry
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