Distributed test pattern generation

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371 2231, G06F 1100

Patent

active

058020756

ABSTRACT:
A method and apparatus for automatically generating test patterns for a circuit design using a number of data processing elements. The present invention reduces the wall time required to generate the test patterns for the overall circuit design by partitioning the design into a number of partitions, distributing the partitions to a number of data processing elements, and generating test patterns for each partition on the corresponding data processing elements. The present invention automatically assembles the resulting local test patterns to reflect the scan structure of the overall circuit design.

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