Distributed packet processing architecture for network...

Details Distributed packet processing architecture for network... Distributed packet processing architecture for network...

2005-08-18

2009-10-20

Ho, Duc C (Department: 2419)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S392000, C370S352000, C370S356000, C709S229000

Reexamination Certificate

active

07606245

ABSTRACT:
An access server architecture, and methods for use of the architecture, are disclosed. The architecture and methods are designed to increase the scalability of and balance processor load for a network access server device. In this architecture, packet forwarding and packet processing are distributed amongst the cards serving the low-speed access lines, such that each line card is responsible for performing forwarding and packet processing for packets associated with the low-speed ports that line card serves. As the number of line cards expands, forwarding resources are expanded in at least rough proportion. The NAS route switch controller, and the high-speed ports, are largely relieved of packet processing tasks because the egress port uses a distribution engine that performs a cursory examination on one or more header fields on packets received—comprehending only enough information to allow each packet to be distributed to the appropriate line card for full packet processing.

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