Distributed memory system with ECC and method of operation

Details Distributed memory system with ECC and method of operation Distributed memory system with ECC and method of operation

1996-10-08

1998-07-21

Baker, Stephen M.

Excavating

G06F 1110

Patent

active

057843910

ABSTRACT:
A superscalar microprocessor chip includes a core processor with a distributed memory surrounding the perimeter of the processor. The distributed memory is arranged in sub-memory elements, each memory sub-element including check bits for each word stored in the sub-element. The number of check bits for each word is based upon the check bits required for a memory word formed from each word in each memory subelement, the number of ECC bits required for the combined word being less than the total number of bits available in the distributed memory. The difference in ECC bits and available bits provides spare bits which are used to route the ECC bits to ECC circuity positioned within the distributed memory for single error correction and double error detection. The position of the ECC circuity and the layout of the sub-memory elements with respect to the ECC circuitry are arranged to minimize the travel of the ECC bits for data correction or detection purposes, and does not adversely affect processor cycle time.

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