Distributed machine state controlled processor system with a CPU

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364DIG2, 364950, 3649503, 3649504, G06F 104, G06F 110

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053676629

ABSTRACT:
A controller (MSC) for generating a basic control signal to permit a CPU to access to a resource in a processor system is arranged in each of local control blocks. The MSC is operated not by a basic clock supplied to the CPU but by a clock which is generated prior to the clock supplied to the CPU and which passes through the MSC and is precisely controlled for delay. Thus, the delay of a control signal to be supplied to the CPU relative to the reference clock is minimized and a high speed operation of the system is attained.

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Intel Microprocessor and Peripheral Hand Book, vol. I 1987, 3-34 to 3-35.

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