Distributed interlock apparatus and distributed interlock manage

Details Distributed interlock apparatus and distributed interlock manage Distributed interlock apparatus and distributed interlock manage

1991-10-03

1992-07-07

Lee, Thomas C.

Boots, shoes, and leggings

364DIG1, 364DIG2, 364228, 364229, 3642292, 364230, 3642426, 3649314, 36493541, G06F 1314, G06F 1200

Patent

active

051290898

ABSTRACT:
Interlocking of addresses in a system with parallel processors using a common memory space is managed by maintaining for each processor a record of the lock state of the system. When a processor seeks to initiate a transaction, the transaction is analyzed against the lock state record, and the processor's request for access to an intercommunication bus is transmitted only when the lock state of the system is in condition to process the transaction. By monitoring and analyzing bus transactions, the lock state record of each processor is maintained up to date. By thus blocking a transaction involving a locked address before the bus is requested, the tying up of the bus in futile activity is avoided.

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patent: 4574350 (1986-03-01), Starr
patent: 4937733 (1990-06-01), Gillett, Jr. et al.
Sahni, "Crosspoint Cache Architectures", Proceedings of the 1987 International Conference on Parallel Processing (Aug. 1987) pp. 268-269.
Ghosal et al., "Shamp: An Experimental Shared Memory Multimicroprocessor System and Performance Evaluation of Parallel Algorithms", Microprocessing and Microprogramming 19 (1987), pp. 179-192.
Muhlemann, "Method for Reducing Memory Conflicts Caused by Busy Waiting in Multiple-Processor Synchronisation", IEE Proc., vol. 127, pt. E, No. 3 (May 1980), pp. 85-87.

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