Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Frequency or repetition rate conversion or control
Reexamination Certificate
2001-09-21
2002-09-24
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Frequency or repetition rate conversion or control
C327S427000, C333S104000
Reexamination Certificate
active
06456125
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to improvement on bias supply by being equipped with a bias bypass line independent from a signal line in a distributed high frequency circuit in which outputs of a plurality of transistors are connected in parallel to each other, more particularly, to a distributed high frequency circuit amplifying a microwave or millimeter wave signal, or mixing a local oscillation wave into an RF (Radio Frequency) or IF (Intermediate Frequency) signal.
2. Description of the Related Art
FIG. 7
shows a transmitter
10
of a base station for a portable telephone.
An IF signal and an local oscillation (Local Oscillator) signal are provided to a mixer
11
to generate an RF (Radio Frequency) signal, which is amplified to a large signal by a low noise amplifier
12
and a high-power amplifiers
13
and
14
connection in cascade, and in turn provided to an antenna not shown. Since amplifiers of such a transmitter
10
are required to have large current driving ability, the amplifier has amplifying transistors connected in parallel.
FIG. 8
shows such a prior art distributed high frequency amplifier
20
W.
A high frequency signal provided to an input IN is equally distributed through a capacitor
21
and a power splitter circuit
22
to the gates of transistors
23
A and
23
B connected in parallel. The power splitter
22
also plays a role as an impedance matching circuit. In order to supply biases to the gates of the transistors
23
A and
23
B such that a high frequency signal does not leak to a gate bias input G, a resistor
24
is connected between the gate bias input G and the gate of the transistor
23
A. A resistor
25
for bias adjustment is connected between the gate bias input G and ground. A bias is provided to the gate of the transistor
23
B through the resistor
24
and a line of the power splitter circuit
22
. The resistance value of the resistor
24
is determined such that a large variation of the bias does not arise by leaking through the resistor
24
when a signal with a large amplitude is propagating for the gates of the transistors
23
A and
23
B. A resistor
26
connected between the gates of the transistors
23
A and
23
B works to stabilize signals provided to the gates of the transistors
23
A and
23
B in a case where these signals are unbalanced, and each has the resistance value of several ohms. The capacitor
21
is employed to block the gate bias to leak out on the input IN side.
The drains of the transistors
23
A and
23
B are connected through a power superimposition circuit
27
W and a capacitor
28
to an output OUT. The power superimposition circuit
27
W also plays a role as an impedance matching circuit. In order to apply a bias voltage to the drains of the transistors
23
A and
23
B, a drain bias transmission line
29
WB is connected between a drain bias input terminal DB and the output of the power superimposition circuit
27
W and a capacitor
30
B is connected to an end of the drain bias transmission line
29
WB. The length of the drain bias transmission line
29
WB is &lgr;/4, where &lgr; denotes a signal wavelength. The capacitor
30
B is used for signal grounding. With the drain bias transmission line
29
WB and the capacitor
30
B, the impedance of the drain bias transmission line
29
WB side measured at a node N
0
between the power superimposition circuit
27
W and a capacitor
28
is infinite in an ideal case, thereby blocking a signal to flow to the drain bias transmission line
29
WB side from the node N
0
. The capacitor
28
is used to block a drain bias to leak out to the output OUT.
In order to increase the output power of the distributed high frequency amplifier
20
W, it is required to increase the drain currents of the transistors
23
A and
23
B. When the distributed high frequency amplifier
20
W is formed in an MMIC (Monolithic Microwave Integrated Circuit), a metal film of a line is thin and sheet resistance thereof is comparatively large, so the line width is required to be wide such that a voltage drop caused by a resistance component is reduced. The line width of the drain bias transmission line
29
WB is required to be wide since the drain current for the two transistors
23
A and
23
B flows therethrough. Further, since the drain current flows through the power superimposition circuit
27
W, the width of a current path thereof also has to be wider.
However, since the power superimposition circuit
27
W is necessary to work as the matching circuit as well, the line width thereof is limited. Further, the impedance of the drain bias transmission line
29
WB side measured at the node N
0
is actually finite and a high frequency signal leaking out to the drain bias transmission line
29
WB side from the node N
0
is proportional to the ratio of the impedance of the configuration from which the drain bias transmission line
29
WB is removed measured at the node N
0
to the impedance of the drain bias transmission line
29
WB side from the node NO. Hence, the position of the node N
0
is preferably closer to the drain electrodes of the transistors
23
A and
23
B each with a relatively small impedance. In other words, since the node N
0
is disposed apart from the drain electrodes of the transistors
23
A and
23
B, a signal is leaked out to the drain bias transmission line
29
WB side from the node NO.
FIG. 9
shows a configuration to be able to solve such problems, wherein one ends of drain bias transmission lines
29
A and
29
B are connected to the drain electrodes of the respective transistors
23
A and
23
B so as to be close thereto. The other end of the drain bias transmission line
29
A is connected to a drain bias input DA, on one hand, and grounded through a capacitor
30
A, on the other hand. Likewise, the other end of the drain bias transmission line
29
B is connected to the drain bias input terminal DB, on one hand, and grounded through the capacitor
30
B, on the other hand.
In such a configuration, since no drain bias current flows through the power superimposition circuit
27
, the line width of the power superimposition circuit
27
can be designed freely such that the power superimposition circuit
27
functions sufficiently as a matching circuit. Further, each width of the drain bias transmission lines
29
A and
29
B can be half that of the drain bias transmission line
29
WB of
FIG. 8
since the value of drain current flowing through each of the drain bias transmission lines
29
A and
29
B is half that of the drain bias transmission line
29
WB of FIG.
8
. Furthermore, signals leaked out into the drain bias transmission lines
29
A and
29
B from nodes NA and NB can be reduced.
However, since the two drain bias inputs DA and DB are required to be provided on both sides of the circuit, wiring of the drain bias transmission lines between a plurality of distributed amplifiers are complex in a case where the plurality of distributed amplifiers are cascaded as shown in FIG.
7
.
FIG. 10
shows a configuration to be able to solve such a problem, wherein the drain bias is only provided from the drain bias input terminal DB. However, the drain current to the transistor
23
A flows through the power superimposition circuit
27
W; therefore the line width of the power superimposition circuit
27
W is necessary to be wider, which disables the line width to be freely designed such that the power superimposition circuit
27
W works sufficiently as the matching circuit. Further, it is necessary to flow a drain current into the drain bias transmission line
29
WB for the two transistors
23
A and
23
B, and it is necessary to make the drain load of the transistor
23
A be equal to that of the transistor
23
B; therefore the line width of the drain bias transmission lines
29
WA and
29
WB have to be double that of the drain bias transmission lines
29
A and
29
B of
FIG. 9
, leading to increase in chip area.
FIG. 11
shows a layout in a case where the circuit of
FIG. 10
is formed in an MMIC.
All the parts of
FIG. 11
are enc
Armstrong Westerman & Hattori, LLP.
Fujitsu Quantum Devices Limited
Tran Toan
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