Distributed digital signal processing system using standard reso

Details Distributed digital signal processing system using standard reso Distributed digital signal processing system using standard reso

1990-07-19

1991-12-31

Moore, David K.

Image analysis

Histogram processing

For setting a threshold

358443, G06K 900

Patent

active

050778102

ABSTRACT:
A digital processing architecture for a high resolution image sensor uses a plurality of like digital processors for time-divided processing of the output of the sensor. Each processor is operational according to start and stop signals from a programmable sequencer. In a preferred embodiment, two sets of processors handle a line resolution of 1024 pixels, one set doing the first half of each line and the other set doing the second half. This is of particular utility where vertical processing is required, and the full line delays needed are divided into partial resettable delays resident in each of the processors.

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Mattausch, H. et al., "A Memory Based High-Speed Digital Delay Line with a Large Adjustable Length," IEEE Journal of Solid State Circuits, vol. SC-23, No. 1, pp. 105-110, Feb. 1988.

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