Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1999-12-09
2003-11-04
Cangialosi, Salvatore (Department: 2661)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S236000
Reexamination Certificate
active
06643294
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to cell relay systems and, more particularly, to a cell relay switch with a merged buffer architecture.
BACKGROUND OF THE INVENTION
Asynchronous transfer mode (ATM) switches provide high-speed data exchange while minimizing the impact on overall system bandwidth. ATMs are commonly used in local area networks (LANs) and wide area networks (WANs). Recently, however, ATM switches have been used in wideband data transfer protocols, such as synchronous optical network (SONET) and synchronous transport stream (STS) systems.
FIG. 1
is a block diagram of a conventional ATM switch
100
. The switch
100
includes several input ports
110
, several output ports
120
, optical-to-digital (O/D) converters
130
, digital-to-optical (D/O) converters
140
, switching fabric
150
, and controller
160
. The input ports
110
receive data packets, including one or more cells, from a source on a corresponding set of high-speed optical input channels
115
. The output ports
120
output the received cells to a destination on a corresponding set of high-speed optical output channels
125
.
The OLD converters
130
connect to the input ports
110
to convert the received cells from optical signals to digital signals. The D/O converters
140
connect to the output ports
120
to convert the cells from digital signals back into optical signals for transmission by the output ports
120
on the output channels
125
. The switching fabric
150
connects between the O/D and D/O converters
130
and
140
. The switching fabric
150
transmits the received cells from an input port
110
to an appropriate output port
120
in response to a control signal from the controller
160
. The controller
160
is a programmable device that controls the routing of the cells through the switch
100
.
Cells arrive at the input ports
110
during a period called a time slot. In an ATM environment, the cells include a 5-octet header and a 48-octet information field. When a cell arrives at an input port
110
, the controller
160
decodes the cell's header to determine the proper output port
120
for the cell. The controller
160
then configures the switching fabric
150
to transmit the cell to this output port
120
. When such a cell arrives at a single input port
110
destined for a single output port
120
, the cell is called a “unicast” or “point-to-point” cell. A “multicast” cell, on the other hand, arrives at a single input port
110
destined for several of the output ports
120
. In contrast, a “broadcast” cell arrives at a single input port
110
destined for all of the output ports
120
.
When several cells arrive at different input ports
110
destined for the same output port
120
, conflicts or contentions result. Cell contention introduces throughput limitations, slowing the operation of the switch
100
.
In addition, ATM protocol mandates that a switch
100
transmit cells from its output ports
120
in the same order that they arrived at its input ports
110
. This makes the switch
100
effectively transparent to the communication medium by assuring that packets of arriving cells are not reordered when they leave the switch
100
. With cells arriving on several different input ports
110
during each time slot, often contending for the same output ports
120
, maintaining cell sequence and high throughput rates becomes difficult.
To address these deficiencies, conventional ATM switch architectures employ output-buffering, input-buffering, or shared memory techniques to facilitate data flow and maintain cell sequence between the input ports and the output ports.
FIG. 2
is a block diagram of a conventional switch
200
employing the output-buffering technique. The switch
200
includes several input ports
210
, several output ports
220
, several output buffers
230
, and a controller
240
.
Each of the input ports
210
connects to all of the output buffers
230
. The output ports
220
, however, connect to only a single dedicated buffer
230
. As a result, the buffers
230
contain multiple inputs and a single output. The controller
240
is a content addressable memory (CAM) controller that controls the operation of the buffers
230
.
When a cell arrives at one of the input ports
210
, the controller
240
decodes the cell's header and instructs a particular one of the output buffers
230
, corresponding to the designated output port
220
, to store the cell. When the arriving cell is a multicast or broadcast cell, however, the controller
240
instructs several or all of the corresponding buffers
230
to store the cell during the time slot. If, for example, N cells destined for the same output port
220
arrive at different or all of the input ports
210
, the controller
240
instructs the corresponding buffer
230
to store the N cells during a single time slot. To accomplish this, the switch
200
slows down its throughput rate N times. As a result, the per-port rate of output-buffered ATM switches, such as switch
200
, becomes limited by the number of input ports
210
.
Another conventional architecture is the input-buffering architecture.
FIG. 3
is a block diagram of a conventional switch
300
employing the input-buffering technique. The switch
300
includes several input ports
310
, several output ports
320
, several-input buffers
330
, a circuit switch matrix
340
, and a controller
350
.
Each of the input ports
310
connects to a dedicated one of the input buffers
330
. The output ports
320
, however, connect to all of the buffers
330
via the circuit switch matrix
340
. The switch matrix
340
connects the input buffers
330
to the output ports
320
based on control signals from the controller
350
. The controller
350
is a CAM controller that controls both the buffers
330
and the circuit switch matrix
340
.
When a cell arrives on an input port
310
, the input port
310
writes the cell directly into its dedicated input buffer
330
. The controller
350
decodes the cell's header and controls the switch matrix
340
to route the cell to the correct output port
320
.
As with output-buffered architectures (e.g., FIG.
2
), input-buffered ATM configurations suffer from reduced throughput. For example, assume that a first cell arrives at a first input buffer
330
for multicasting to two output ports
320
. Assume also that second and third cells stored in other buffers
330
contend for the same two output ports
320
. In this case, the first buffer
330
stores the first cell until the two output ports
320
become available. Because each buffer
330
can only transmit a single cell during any given time slot, the first buffer
330
cannot transmit the cells to both output ports
320
during the same time slot. Thus, the throughput becomes limited by the number of output ports
320
.
Another conventional architecture is the shared-memory ATM architecture.
FIG. 4
is a block diagram of a conventional switch
400
employing the shared memory technique. The switch
400
includes several input ports
410
, several output ports
420
, a shared buffer
430
, and a controller
440
.
Each of the input ports
410
and output ports
420
connect to the shared buffer
430
. The shared buffer
430
is a common memory that stores and outputs cell data based on control signals from the controller
440
. The buffer
430
efficiently stores the cells by permitting active input ports
410
to use the memory space of inactive input ports
410
. The controller
440
is a CAM controller that controls the operation of the buffer
430
.
Like the other conventional switches
100
-
300
, the shared memory switch
400
also has its limitations. For example, during each time slot, the shared buffer
430
can only store N cells and output N cells, where N is the number of the input and output ports
410
and
420
. This again results in reduced throughput by a factor of N.
The primary disadvantage of each of the above architectures is that the per-port bandwidth is limited by the number N of input and/or output
Cooperman Michael
Gee Nee-Ben
Rathke John E.
Cangialosi Salvatore
Suchyta Leonard Charles
Verizon Laboratories Inc.
Weixel James K.
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