Distributed control architecture with post and wait logic

Details Distributed control architecture with post and wait logic Distributed control architecture with post and wait logic

1977-10-20

1979-04-10

Chapnick, Melvin B.

Boots, shoes, and leggings

G06F 918, G06F 1516

Patent

active

041492439

ABSTRACT:
Distributed control architecture for a multiprocessor system includes a control processor operating on system programming instructions for executing system supervisory and task management functions, and a control bus over which it outputs execute instruction words containing a pointer address. Program storage stores threaded link lists of intermediate level instruction words, each list head being pointed to by the pointer address of respective execute instruction words. A first subunit processor for executing a first type function has a control input connected to a first distributed control interface processor and includes first post and wait logic for posting a signal indicating completion of a first type function. The first distributed control interface processor has a control input connected to the control bus for receiving the execute instruction word and a data input connected to program storage for accessing intermediate instruction words from a link list pointed to by the pointer address in the execute instruction word, and includes stored control programs to execute first type functions, each accessed by a respective intermediate instruction word. Each control program includes control words sequentially output to the first subunit processor. A second subunit processor controlled by a second distributed control interface processor executes a second type function in a manner similar to the first subunit processor, and includes second post and wait logic for posting a signal to the first subunit processor's post and wait logic indicating completion of a second type function, and a corresponding operation is performed by the first subunit processor's post and wait logic to coordinate execution of mutually dependent first and second type subunit functions. Thus, the control processor can initiate tasks to be performed by the first and second subunit processors and then be free to execute system supervisory and task management functions while the first and second type subunit functions are performed under control of the first and second distributed control interface processors.

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J. K. Boggs, Jr. et al., "Input/Output Channel Mechanism For Handling Control Unit Busy Status" in IBM Tech. Discl. Bull, vol. 19, No. 7, Dec. 1976; pp. 2488-2490.
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