Wave transmission lines and networks – Coupling networks – With impedance matching
Reexamination Certificate
2000-07-17
2002-05-14
Pascal, Robert (Department: 2817)
Wave transmission lines and networks
Coupling networks
With impedance matching
C330S053000
Reexamination Certificate
active
06388540
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a distributed constant circuit, a high-frequency circuit and a bias applying circuit using the same, and an impedance adjusting method.
2. Description of the Background Art
In recent years, as mobile communication has been rapidly developed, electronic waves having a great many frequencies have been required for the communication, and the frequencies of the electronic waves used in the mobile communication are shifting to a microwave band. Therefore, an amplifier used for a portable machine is constituted by a monolithic microwave integrated circuit (MMIC) and a microwave integrated circuit (MIC) modularized.
As anamplifier for amplifying a signal having a desired frequency, a bias applying circuit for applying a predetermined DC bias to the gate and the drain of a field-effect transistor (FET) is used. The bias applying circuit is constituted by a distributed constant line (hereinafter referred to as a &lgr;/4 line) having a length which is one-fourth the wavelength of a fundamental wave, for example.
When one end of the &lgr;/4 line is short-circuited to a ground potential in an AC manner, the other end thereof enters an open state with respect to the frequency of the fundamental wave (hereinafter referred to as a fundamental frequency). The &lgr;/4 line is widely applied to various types of circuits such as a distributor, a synthesizer, a directional coupler, and a filter in addition to the bias applying circuit to the FET.
However, the lower the fundamental frequency is, the larger the length of the &lgr;/4 line is, thereby increasing the size of a chip or a module at frequencies which are not more than several gigahertz. Therefore, a method of miniaturizing the &lgr;/4 line has been examined.
FIG. 37
is a diagram showing a &lgr;/4 line, and
FIG. 38
is a diagram showing a conventional distributed constant circuit equivalent to the &lgr;/4 line. In
FIG. 37
, Z
0
is the characteristic impedance of a &lgr;/4 line 100, and L
0
is the length of the &lgr;/4 line
100
. In
FIG. 38
, Z
1
is the characteristic impedance of a line
101
, L
1
is the length of the line
101
, and C
1
is the capacitance value (capacitance) of capacitors
102
and
103
.
In the distributed constant circuit shown in
FIG. 38
, the line
101
is connected between a node NA and a node NB, the node NA is grounded through the capacitor
102
, and the node NB is grounded through the capacitor
103
.
If the characteristic impedance Z
1
, the length L
1
and the capacitance value C
1
satisfy relations expressed by the following equations (12) and (13), the distributed constant circuit shown in
FIG. 38
is equivalent to the &lgr;/4 line
100
shown in
FIG. 37
at a fundamental frequency (see an article entitled by Tetsuo Hirota, Akira Minakawa, Masahiro Muraguchi, “Reduced-Size Branch-Line and Rat-Race Hybrids for Uniplanar MMIC's”, IEEE MTT. Vol. 38, No. 3, March 1990):
Z
1
=
Z
0
sin
2
π
λ
L
1
(
12
)
C
1
=
1
ω
Z
0
cos
2
π
λ
L
1
(
13
)
where &lgr; is the wavelength of a fundamental wave, and &ohgr; is the angular velocity of the fundamental wave. In the foregoing equations (12) and (13), the length L
1
of the line
101
can be arbitrarily selected, so that the length L
1
of the line
101
can be reduced.
FIG. 39
is a circuit diagram of a bias applying circuit using the distributed constant circuit shown in
FIG. 38. A
bias applying circuit
110
shown in
FIG. 39
functions as a drain bias applying circuit for applying a drain bias V
dd
to a FET
200
.
In the bias applying circuit
110
shown in
FIG. 39
, a line
101
is connected between a node NA and a node NB, and the node NA is grounded through a capacitor
111
. The drain bias V
dd
is applied to the node NA. The node NB is grounded through a capacitor
103
, and is connected to the drain of the FET
200
.
Z
1
is the characteristic impedance of the line
101
, and L
1
is the length of the line
101
. C
1
is the capacitance value of the capacitor
103
, and C
g
is the capacitance value of the capacitor
111
. Z
fr
is an impedance in a case where an input side (a terminal A) is viewed from the node NB, and Z
lo
is an impedance in a case where an output side (a terminal B) is viewed from the node NB. The impedance Z
fr
and the impedance Z
lo
are taken as 50&OHgr;.
The capacitor
111
has a sufficiently small impedance relative to the fundamental frequency. Therefore, the node NA is short-circuited to a ground potential in an AC manner. Consequently, the node NB enters an open state with respect to the fundamental frequency. That is, the bias applying circuit
110
shown in
FIG. 39
functions as a &lgr;/4 line with respect to the fundamental frequency. In this case, the drain bias V
dd
is applied to the node NA.
On the other hand, when the &lgr;/4 line
100
of
FIG. 37
is used as a drain bias applying circuit to the FET, one end of the &lgr;/4 line
100
is grounded through a capacitor, and the other end is connected to the drain of the FET. In this case, the other end of the &lgr;/4 line
100
enters an open state with respect to the fundamental frequency, and enters a short-circuited state with respect to even-order harmonics.
It has been known that in load conditions under which a short-circuited state occurs with respect to even-order harmonics (particularly second harmonics) in a B-class operation, the power-added efficiency of an amplifier which is constituted by a FET is improved. When the A /4 line
100
is used as a bias applying circuit, therefore, the efficiency of the amplifier can be increased.
In a case of an A-class or AB-class operation of an amplifier, however, the conditions are not necessarily most suitable. In this case, it is necessary to adjust a harmonic impedance (particularly second harmonics) such that the characteristics of the amplifier are most suitable (see “A Load Pull system with Harmonic Tuning”, Microwave Journal, pp. 128-132, March 1996).
Meanwhile, when the distributed constant circuit shown in
FIG. 38
is used as a bias applying circuit for a B-class amplifier as shown in
FIG. 39
, the node NB does not enter a short-circuited state with respect to even-order harmonics. Although an amplifier can be miniaturized, therefore, high efficiency of a B-class amplifier cannot be achieved.
Further, when the distributed constant circuit is used for an A-class or AB class operation, high efficiency can not be achieved because a harmonic impedance is fixed.
In the amplifier which is constituted by the FET, the FET may, in some cases, oscillate in a high-frequency region. As measures to prevent the FET from oscillating, there is a method of significantly decreasing gain at an oscillation frequency. When the &lgr;/4 line
100
shown in
FIG. 37
is used as a bias applying circuit, the gain of the amplifier can be decreased at even-order harmonics, while the gain thereof at the other frequencies cannot be decreased. Therefore, a bias applying method capable of decreasing gain at an arbitrary frequency is demanded.
Furthermore, in an amplifier and a mixer, spurious (a signal having an unnecessary frequency) may, in some cases, be a problem. Therefore, measures to suppress spurious signals is demanded.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a distributed constant circuit which has characteristics equivalent to a &lgr;/4 line with respect to a fundamental wave, can be miniaturized, and can suppress an arbitrary frequency, and a high-frequency circuit using the same.
Another object of the present invention is to provide a bias applying circuit which can be miniaturized and increased in efficiency.
Still another object of the present invention is to provide an impedance adjusting method for adjusting a load impedance of a transistor in a bias applying circuit.
A further object of the present invention is to provide a distributed constant circuit which can be miniaturized and lowered in cost.
A distributed cons
Nishida Masao
Uda Hisanori
Akin Gump Strauss Hauer & Feld L.L.P.
Jones Stephen E.
Pascal Robert
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