Distributed clocking system

Pulse or digital communications – Synchronizers

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375371, 370518, 327144, A04L 700

Patent

active

058704418

ABSTRACT:
A clocking mechanism with improved fault tolerance for synchronizing a distributed processing system includes a plurality of distributed clock sources. Each clock source may operate as a master clock for synchronizing the operations of the entire system or as a slave to an external clock while remaining available, in a backup capacity, to operate as a master clock in the event of a failure in the previous master clock. A clock selection mechanism is provided in each distributed switch element for selecting the best clock available to each switch element for synchronization. A failure recovery mechanism is provided with fast and automatic recovery in the event of a failure in a master clock. A data extraction mechanism is also provided capable of sampling a bit stream that is not phase-aligned, even in the presence of timing jitter and pulse width distortion, and having provisions for detecting a bit slip.

REFERENCES:
patent: 4142069 (1979-02-01), Stover et al.
patent: 4173713 (1979-11-01), Giesken et al.
patent: 4201889 (1980-05-01), Lawrence et al.
patent: 4201891 (1980-05-01), Lawrence et al.
patent: 4317962 (1982-03-01), Cox et al.
patent: 4736393 (1988-04-01), Grimes et al.
patent: 4817085 (1989-03-01), De Prycker
patent: 4903260 (1990-02-01), Boettle et al.
patent: 4916690 (1990-04-01), Barri
patent: 4939752 (1990-07-01), Literati et al.
patent: 4998275 (1991-03-01), Braunstein et al.
patent: 5058140 (1991-10-01), Johnson
patent: 5068877 (1991-11-01), Near et al.
patent: 5153874 (1992-10-01), Kohno
patent: 5197086 (1993-03-01), Jackson et al.
patent: 5259006 (1993-11-01), Price et al.
patent: 5313501 (1994-05-01), Thacker
patent: 5509037 (1996-04-01), Bucker et al.
patent: 5577075 (1996-11-01), Cotton et al.
Barri, et al. "Implementation of a 16 to 16 Switching Element for ATM Exchanges", IEEE Journal On Selected Areas in Communications, vol. 9, No. 5, pp. 751-757, Jun. 1991.
Eckberg, et al. "Effects of Output Buffer Sharing on Buffer Requirements in an ATDM Packet Switch", AT&T Bell Laboratories, Holmdel, New Jersey 07733, pp. 459-465, IEEE 1998.
Horstmann, et al. "Metastability Behavior of CMOS ASIC Flip-Flops in Theory and Tests", IEEE Journal of Solid Circuits, vol. 24, No. 1, pp. 146-157, Feb., 1989.
Karol, et al. "Imput v. Output Queuing on a Space-Division Packet Switch", IEEE Global Telecommunications Conference, Conference Record, vol. 2, Session 19.4, pp. 659-665, Dec. 1986.
Kleeman, et al. "Metastable Behavior in Digital Systems" IEEE Design & Test of Computers, pp. 4-19, Dec. 1987.
Kuwahara, et al. "A Shared Buffer Memory Switch for an ATM Exchange", pp. 118-122, IEEE, 1989.
Sakurai, et al. "Large-Scale ATM Multistage Switching Network with Shared Buffer Memory Switches", IEEE Communications, vol. 29, No. 1, pp. 90-96, Jan. 1991.
Van Malderen "System 12: Review of the Fundamental Concepts", Electrical Communication, vol. 59, No. 1, pp. 20-28, 1985.
Veendrick "The Behavior of Flip-Flops Used as Synchronizers and Prediction of Their Failure Rate", IEEE Journal of Solid-State Circuits, vol. SC-15, No. 2, pp. 169-176, Apr., 1980.

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