Distributed clock tree scheme in semiconductor packages

Details Distributed clock tree scheme in semiconductor packages Distributed clock tree scheme in semiconductor packages

1991-08-14

1992-11-17

Lee, John D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

257786, H01L 2302, H01L 2312

Patent

active

051648172

ABSTRACT:
A clock plane is embedded in the housing of a semiconductor chip package where the plane is connected to two or more clock pads on the semiconductor die through vias, bonding fingers and bonding wires. The two or more clock pads are connected by one or more clock lines. The clock plane is connected by means of a via to a clock iput pin. In this manner, a clock signal fed to the clock input pin is driven through the one or more clock line with its tributaries from two separate locations by two or more input clock pads. This reduces clock skew and permits a smaller area of the die surface to be taken up by the clock lines.

REFERENCES:
patent: 4427991 (1984-01-01), Yamamura et al.

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