Distributed circuits to turn off word lines in a memory array

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

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Details

36523001, 365204, 365203, G11C 700

Patent

active

061446106

ABSTRACT:
A memory device that includes a row decoder, a set of word line, and one or more word line pull-down drivers. The row decoder includes decoding circuitry and a set of word line drivers. The decoding circuitry is configured to receive address information and generate a set of word line control signals. The word line drivers couple to the decoding circuitry and are responsive to the word line control signals. Each word line driver is configured to provide pull-up drive capability, and can further be configured to provide pull-down drive capability. Each word line couples to at least one word line driver. The word line pull-down driver(s) couples to the word lines, with each word line pull-down driver being configured to provide pull-down drive capability. One or more word line pull-down drivers can be distributed (i.e., uniformly) along the length of each word line. The word lines can also be implemented using a hierarchical word line architecture that includes a set of main word lines (i.e., fabricated on a metal layer) and a set of segmented word lines (i.e., fabricated on a polysilicon layer) coupled to each main word line.

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