Distributed capacitance estimations of interconnects within inte

Details Distributed capacitance estimations of interconnects within inte Distributed capacitance estimations of interconnects within inte

1997-03-31

1999-07-13

Kemper, Melanie A.

Boots, shoes, and leggings

364488, 39530035, 39550006, G06F 1750

Patent

active

059235683

ABSTRACT:
A method of estimating the distributed capacitance of an interconnection line within an integrated circuit. The invention includes a method for estimating distributed capacitance between interconnection lines within an integrated circuit. The integrated circuit is modeled as including a middle plane which is planar and adjacent to a top plane and a bottom plane. Each plane includes a plurality of interconnection lines which are infinite in length and parallel. The interconnection lines of the middle plane are orthogonal to the interconnection lines of the top plane and the interconnection lines of the bottom plane. A ground plane is adjacent and planar to the bottom plane. A first value of capacitance between an interconnection line of the middle plane and an interconnection line of the top plane is estimated ignoring the effects of the bottom plane. A second value of capacitance between the interconnection line of the middle plane and the interconnection line of the top plane is estimated assuming the bottom plane is a solid conductive sheet. An actual value of capacitance between the interconnection line of the middle plane and the interconnection line of the top plane is estimated by interpolating between the first value of capacitance and the second value of capacitance. The invention simplifies the required calculations by breaking a three array structure into two separate two array structures. Similarly, an actual value of capacitance between the interconnection line of the middle plane and the ground plane, an actual value of capacitance between the interconnection line of the middle plane and an interconnection line of the bottom plane, and an actual value of capacitance between two interconnection lines of the middle plane can be estimated.

REFERENCES:
patent: 5610833 (1997-03-01), Chang et al.
patent: 5706206 (1998-01-01), Hammer et al.
Arora et al., "Modeling and Extraction of Interconnect Capacitances for Multilayer VLSI Circuits" IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, v. 15, n. 1 pp. 58-67, Jan. 1996.
Raphael--Interconnect Analysis Program; Version 2.1; Integrated Circuit Business Division, Palo Alto--Hewlett-Packard Company; Aug. 17, 1993.

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