Distributed cache in dynamic rams

Details Distributed cache in dynamic rams Distributed cache in dynamic rams

1984-09-18

1988-02-16

Harkcom, Gary V.

Boots, shoes, and leggings

365189, 365230, G11C 700

Patent

active

047259450

ABSTRACT:
A microcomputer memory system is organized into a plurality of banks (16). Each back consists of an array of static column mode dynamic random access memories (DRAMs) of the type having an on-chip static buffer for storing an entire row. The static buffers associated with each bank functions as a distributed cache (24) to hold the last accessed row for the associated bank. A memory controller (18) receives real addresses from a CPU (10) or other device on the memory bus (14) and extracts bank and row numbers from the address. The memory controller determines whether the accessed row for a memory bank is in the distributed cache and, if it is, accesses the distributed cache for that bank. Otherwise, the memory controller switches the contents of the distributed cache with the contents of the addressed row for that bank.

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