Distributed balanced frequency multiplier

Details Distributed balanced frequency multiplier Distributed balanced frequency multiplier

2001-07-13

2002-11-05

Lee, Benny (Department: 2817)

Wave transmission lines and networks

Frequency multipliers

C327S119000

Reexamination Certificate

active

06476692

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a distributed balanced frequency multiplier, more particularly, to a distributed balanced frequency multiplier, for use in microwave or millimeter-wave applications, comprising two transistors as non-inverting and inverting amplifiers constructed by asymmetric connections with respect to each other, and means for correcting a transfer characteristic difference therebetween in high frequencies.
2. Description of the Related Art
FIG. 7
is a circuit diagram of a prior art distributed balanced frequency multiplier circuit. This circuit is analogous to one disclosed in Japanese Patent Publication No. 2807508 B.
A fundamental signal SI having a frequency f is provided to a signal input
10
. The input signal SI propagates to a branch point J
1
, and is provided therefrom to the gate G of a FET
15
A and the source S of a FET
15
B through first and second input transmission lines, respectively. The source S of the FET
15
A is grounded and the gate G of the FET
15
B is AC grounded through a capacitor
18
. Current signals from the drains D of the FETs
15
A and
15
B propagates through first and second output transmission lines, respectively, of a joining section to a connection point J
2
to be taken out as a signal SO from a signal output
21
.
Each gate G of the FETs
15
A and
15
B is biased at about a pinch-off voltage, and the drain current signals of the FETs
15
A and
15
B have about half-rectified waveforms. Since the source of the FET
15
A is grounded and a signal is provided to the gate thereof, the FET
15
A operates as a non-inverting amplifier amplifying a nearly positive half of the input signal. Whereas since the gate of the FET
15
B is AC grounded through the capacitor
18
and a signal is provided to the source thereof, the FET
15
B operates as an inverting amplifier amplifying a nearly negative half of the input signal.
Hence, in an ideal case, a fundamental and odd harmonics included in the drain current of the FET
15
A have reverse phases to respective those of a fundamental and odd harmonics included in the drain current of the FET
15
B to cancel out at the join, with the result that none of them are taken out from the signal output
21
. Whereas even harmonics included in the drain current of the FET
15
A have the same phases and amplitudes as respective those of the FET
15
B, and therefore they are added to each other at the join, with the result that only the added even harmonics are taken out from the signal output
21
.
Since the amplitude of a fourth order harmonic is considerably smaller compared with that of a second harmonic, the circuit of
FIG. 7
is employed as a frequency doubler.
As shown in
FIG. 7
, by using the FETs
15
A and
15
B having grounded source and gate, respectively, there is no need to equip, at an input section, a large scale hybrid circuit for generating two fundamentals in reverse phase to each other using an input signal SI. Therefore, the balanced frequency multiplier of
FIG. 7
has an advantage of downsizing.
However, the present inventor found that when providing the input signal SI having a frequency of the order of 10 GHz or higher to the balanced frequency multiplier of
FIG. 7
, a difference in output amplitudes between the FETs
15
A and
15
B arises and thereby cancellation between fundamentals and between odd harmonics deteriorates with weakening even harmonics at the signal output
21
.
FIG. 2
shows power spectra of output signals SO obtained by simulation, wherein square □ denotes the spectrum regarding the circuit of
FIG. 7
, in a case where a fundamental frequency is 38 GHz.
The present inventor has found as a result of analysis that the cause of the above described problem is asymmetric connection between the FETs
15
A and
15
B, that is, although there is no problem in low frequencies, an influence of different parasitic components of the transistors increases as frequency increases, causing a difference in transfer characteristics between the FETs
15
A and
15
B.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a distributed balanced frequency multiplier capable of suppressing a fundamental and odd harmonics included in an output signal with strengthening even harmonics.
In one aspect of the present invention, there is provided a distributed balanced frequency multiplier comprising: a branching section, having first and second input transmission lines, each of the first and second input transmission lines having first and second ends, the first ends of first and second input transmission lines being coupled to a branch point, distributing a fundamental input signal from the branch point to the first and second input transmission lines; a joining section, having first and second output transmission lines, each of the first and second output transmission lines having first and second ends, the second ends of first and second output transmission line being coupled to a join, synthesizing signals from the first and second output transmission lines at the join; a first transistor, having a control input and a current path, the control input being coupled to the second end of first input transmission line, a first end of the current path being grounded, a second end of the current path being coupled to the first end of first output transmission line; a second transistor, having a control input and a current path, the control input being AC grounded, first and second ends of the current path being coupled to the second end of second input transmission line and the first end of second output transmission line, respectively; and an amplitude attenuating element, for example, an open stab coupled to one of the first input transmission line, the second input transmission line, the first output transmission line, or the second output transmission line.
Although an open stub itself is a phase compensating element, a transfer characteristic of the first or second transistor changes by connecting the open stub to a transmission line on the input or output side of the transistor, and as a result it is considered that the open stub works as an amplitude attenuating element.
The length of an open stub is adjusted such that amplitudes of even harmonics, to be obtained, included in the output signals of the two transistors are almost the same as each other in simulation. Thereby, amplitudes of fundamentals and odd and even harmonics included in the first and second output transmission lines become almost equal to each other in regard to the same frequency components. Further, by performing a prior art phase adjustment method, it is possible to suppress unnecessary fundamental and odd harmonics included in the output and strengthen the amplitudes of even harmonics to be obtained.
Generally, the limitation on the length of the open stub is that it is not an integral multiple of &lgr;/2 when the open stub is connected on the input side of a transistor, and it is not an integral multiple of &lgr;/4 when the open stub is connected on the output side of a transistor.
Other aspects, objects, and the advantages of the present invention will become apparent from the following detailed description taken in connection with the accompanying drawings.


REFERENCES:
patent: 4327343 (1982-04-01), Cornish
patent: 4734591 (1988-03-01), Ichitsubo
patent: 4754244 (1988-06-01), Pavio
patent: 5392014 (1995-02-01), Nishida et al.
patent: 6124742 (2000-09-01), Cook et al.
patent: 60-106208 (1985-06-01), None
patent: 3-158008 (1991-08-01), None

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