Distributed balanced address detection and clock buffer circuitr

Details Distributed balanced address detection and clock buffer circuitr Distributed balanced address detection and clock buffer circuitr

1997-09-12

1999-03-16

Nelms, David

Static information storage and retrieval

Addressing

Sync/clocking

36523008, 36518905, G11C 800

Patent

active

058838546

ABSTRACT:
Disclosed is a method of designing a memory device on a semiconductor chip. The memory device includes a memory array having a depth that defines a number of words and a word width that defines a number of bits. The method of designing the memory device includes partitioning an address transition detect circuit into a plurality of ATD sub-circuits. Partitioning a clock buffer into a plurality of clock buffer sub-circuits. Distributing each of the plurality of ATD sub-circuits to each of the number of bits of the memory array. The method of designing the memory device further includes distributing each of the plurality of clock buffer sub-circuits to each of the number of bits of the memory array. In a further variation, the method may be used to distribute the ATD sub-circuits and the clock buffer sub-circuits to where the clock load is distributed for a particular memory device.

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