Distributed averaging analog to digital converter topology

Details Distributed averaging analog to digital converter topology Distributed averaging analog to digital converter topology

2002-05-24

2003-09-30

Wamsley, Patrick (Department: 2631)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S159000

Reexamination Certificate

active

06628224

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to analog to digital converters (ADC's), and more particularly, to various topologies for high speed analog to digital converters that use interleaving of amplifier connections to reduce parasitic capacitance.
2. Related Art
A subranging analog to digital converter (ADC) architecture is suitable for implementing high-performance ADC's (i.e. high speed, low power, low area, high resolution).
FIG. 1
shows the generic two-step subranging architecture, comprising a reference ladder
104
, a coarse ADC
102
, a switching matrix
103
, a fine ADC
105
, coarse comparators
107
, fine comparators
108
and an encoder
106
. In most cases, a track-and-hold
101
is used in front of the ADC. In this architecture, an input voltage is first quantized by the coarse ADC
102
. The coarse ADC
102
compares the input voltage against all the reference voltages, or against a subset of the reference voltages that is uniformly distributed across the whole range of reference voltages. Based on a coarse quantization, the switching matrix
103
connects the fine ADC
105
to a subset of the reference voltages (called a ‘subrange’) that is centered around the input signal voltage.
Modern flash, folding and subranging analog to digital converters (ADC's) often use averaging techniques for reducing offset and noise of amplifiers used in the ADC. One aspect of averaging is the topology that is used to accomplish averaging, i.e., which amplifier outputs in which arrays of amplifiers are averaged together.
In general, flash, folding and subranging ADC's use cascades of distributed amplifiers to amplify the residue signals before they are applied to the comparators
107
,
108
. These residue signals are obtained by subtracting different DC reference voltages from an input signal V
in
. The DC reference voltages are generated by the resistive ladder (reference ladder)
104
biased at a certain DC current. Two implementation aspects of averaging that should be distinguished are circuit implementation and topology.
With respect to circuit implementation, various ideas have been published in the literature, e.g., connecting resistors between amplifier outputs, and connecting capacitors between amplifier inputs. Interpolation is a type of averaging, and additional published techniques include capacitive interpolation, active interpolation using differential pairs, active interpolation using current mirrors, and active interpolation using current splitting.
In general, little attention has been paid to the second aspect: the averaging topology.
FIG. 2
shows an example of a conventional averaging topology. As may be seen from
FIG. 2
, three arrays of amplifiers are used to effect an averaging topology: an “a” amplifier array, comprising amplifiers a
1
, a
2
, a
3
. . . , a “b” amplifier array, comprising amplifiers b
1
, b
2
, b
3
. . . , and a “c” amplifier array, comprising amplifiers c
1
, c
2
, c
3
. . . . The inputs of the “b” amplifiers combine several outputs of the “a” amplifiers, and the inputs of the “c” amplifiers combine several outputs of the “b” amplifiers. Taking the b
2
amplifier as an example, the b
2
amplifier is connected to amplifiers a
1
, a
2
, a
3
, a
4
through a summer SB
2
. Similarly, the amplifier c
2
is connected to the amplifiers b
2
and b
3
through a summer SC
2
. The amplifier c
2
therefore ultimately combines the outputs of the amplifiers a
1
, a
2
, a
3
, a
4
and a
5
through the amplifiers b
2
and b
3
and the summers SB
2
and SB
3
. Because of this, the weights on the inputs (i.e., the weights on the outputs of the amplifiers a
1
. . . a
5
) are not equal.
Averaging is needed to improve noise and offset performance of the amplifiers. Since the signals are correlated (i.e., add linearly) and the noise is uncorrelated (root mean square addition) the signal to noise ratio (SNR) at the “b” array of amplifiers is nominally unity for each “a” amplifier, and {square root over ( )}4=2 for 4 amplifiers. The downside of this arrangement is that many connections are needed between the “a” array and the “b” array. Another downside of this arrangement is the resulting different weighting coefficients, as discussed above, which detract from the root mean square additive property of noise.
The characteristic aspect of the topology of
FIG. 2
is that averaging is ways performed on a set of neighboring amplifiers. For example, the amplifier b
2
combines the outputs of the amplifiers a
1
, a
2
, a
3
and a
4
, implementing 4× averaging. The amplifier c
2
combines the outputs of amplifiers b
2
and b
3
, implementing 2× averaging. Furthermore, the ‘averaging window’ is optimized separately for each set of connections between two arrays of amplifiers. The averaging window may be considered a one-dimensional spatial filter. See Pan et al.,
IEEE J. of Solid State Circ
. 36(12):1847-1858 (December 2001).
In most publications, the averaging window has an infinite width neglecting edge effects). This is an artifact of the circuit implementation used, i.e., averaging is implemented by connecting resistors between the amplifier outputs. An averaging window with a finite width can be obtained if different circuit implementations are used, e.g., active averaging or capacitive averaging.
In general, finite width averaging windows provide better performance, since they have a smaller edge effect, and they average only across amplifiers that are in their linear region. The disadvantage is that they require many connections between the amplifiers. For example, as shown in
FIG. 2
, each “b” amplifier requires connections to four “a” amplifiers. This results in a considerable layout complexity, which can seriously degrade the ADC performance.
SUMMARY OF THE INVENTION
The present invention is directed to an analog to digital converter topology that substantially obviates one or more of the problems and disadvantages of the related art.
There is provided an analog to digital converter including a first amplifier array connected to taps from a reference ladder and to an input signal, a second amplifier array, wherein each amplifier in the first amplifier array is connected to only two amplifiers of the second amplifier array, a third amplifier array, wherein each amplifier in the second array is connected to only two amplifiers of the third amplifier array, and an encoder connected to outputs of the third amplifier array that converts the outputs to an N-bit digital signal.
In another aspect of the present invention there is provided an analog to digital converter including a reference ladder connected to an input voltage, a first amplifier array connected to taps from the reference ladder, a second amplifier array connected to the first amplifier array in an interleaved manner, a third amplifier array connected to the second amplifier array in an interleaved manner, and an encoder connected to outputs of the third amplifier array that converts the outputs to an N-bit digital signal representing the input voltage.
In another aspect of the present invention there is provided an analog to digital converter including a reference ladder connected to an input voltage, a first plurality of amplifiers connected to taps from the reference ladder, a second plurality of amplifiers connected to the first plurality in an interleaved manner, a third plurality of amplifiers connected to the second plurality in an interleaved manner, and an encoder connected to outputs of the third plurality that converts the outputs to an N-bit digital signal representing the input voltage.
In another aspect of the present invention there is provided an analog to digital converter including a reference ladder, a plurality of amplifier arrays “a”, “b”, “c” . . . “n” arranged in a cascade, wherein the amplifiers in the array “a” are connected to taps from the reference ladder and to an input voltage, a plurality of connections between consecutive arrays of the plurality of amplifier arrays “a”, “b”, “

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