Distributed arithmetic digital processing circuit

Details Distributed arithmetic digital processing circuit Distributed arithmetic digital processing circuit

1981-08-17

1984-05-22

Malzahn, David H.

Boots, shoes, and leggings

G06F 1531

Patent

active

044505337

ABSTRACT:
Digital processing circuit forming a weighted sum of digital signals. It comprises n groups of M series registers (10/1, . . . , 10
M) into which are introduced the signals to be processed, n multiplexers (15/1, 15/2, . . . , 15
), a memory (20) containing precalculated quantities characteristic of the weighted sum to be formed, said memory having a capacity of 2 .sup..beta.+n words distributed into different blocks, a modulo M counter (25), an adder-subtracter (30) connected to the memory, an accumulator-register (40) connected to the adder-subtracter and a clock (50) actuating the counter and the registers. The circuit is in that the memory is subdivided into [M-(2.sup..beta. -M)] blocks of 2.sup.n words and into (2.sup..beta. -M) blocks of 2.sup.n+1 words, said blocks being selected by the bits supplied to the outputs of the counter, in that it comprises supplementary series registers, whose number is at the most equal to 2.sup..beta. -M, said series registers receiving the supplementary signals to be processed and in that it also comprises a multplexing means (21) controlled by the outputs of the counter.

REFERENCES:
patent: 3777130 (1973-12-01), Croisier et al.
patent: 4146931 (1979-03-01), Delforge
patent: 4337518 (1982-06-01), Ohnishi et al.
Tubiana, "Digital Filter" IBM Tech. Disclosure Bulletin vol. 17 No. 9 Feb. 1975 pp. 2656-2658.
Nun, "Versatile Digital Arithmetic Unit with RAMS" Electronic Engineering Jun. 1976, pp. 18-19.

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