Distributed arbitration circuitry for data processing system

Details Distributed arbitration circuitry for data processing system Distributed arbitration circuitry for data processing system

1978-10-25

1980-10-21

Malzahn, David H.

Boots, shoes, and leggings

G06F 946

Patent

active

042297915

ABSTRACT:
A digital data processing system including an interconnection for the various elements that constitute the system. Each element that connects to the interconnection is called a nexus, and each nexus in the system can communicate with other nexuses on a priority basis. A central clocking circuit generates timing signals that control such communications by defining bus cycles on a synchronous basis and each nexus contains priority circuitry that operates in response to these signals. Each nexus that requires access to the interconnection asserts a transfer request signal at a predetermined time during each bus cycle. Priority arbitration circuitry in each nexus receives all such requests and samples them at another, later, time during each bus cycle. When a nexus is transmitting a request and no nexus with a higher priority is transmitting a request, that nexus takes control of the interconnection. A transfer during a subsequent bus cycle to another nexus can be prevented during certain types of transfers.

REFERENCES:
patent: 3983540 (1976-09-01), Keller et al.
patent: 3997896 (1976-12-01), Cassavino, Jr. et al.
patent: 4000485 (1976-12-01), Barlow et al.
patent: 4030075 (1977-06-01), Barlow
patent: 4096569 (1978-06-01), Barlow
Conway, "Approach to Unified Bus Architecture Sidesteps Inherent Drawbacks", Computer Design, Jan. 1977, pp. 71-76.
Bell et al., Computer Engineering A. DEC View of Hardware Systems Design, Digital Press, pp. 269-299, Sep. 1978.

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