Distributed amplifier

Details Distributed amplifier Distributed amplifier

2002-09-30

2004-08-17

Choe, Henry (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including distributed parameter-type coupling

C330S054000, C330S295000

Reexamination Certificate

active

06778015

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a distributed amplifier. For example, the distributed amplifier of the present invention is applied to broadband voltage amplifiers used in optical communications systems or the like.
2. Description of Related Art
Conventionally, distributed amplifiers have been known as amplifiers that amplify broadband signals. For example, the “A 69 GHz broadband Distributed Amplifier” described on page 53 of Preprints of the 2001 Electronics Society Conference of the Electronic Information and Communications Society [Denshi Joho Tsushin Gakkai] (Ogawa et al.) is known as a distributed amplifier.
FIG. 7
is a circuit diagram which shows the construction of such a distributed amplifier. The distributed amplifier
700
comprises source-grounded field effect transistors
701
-
1
through
701
-
8
and gate-grounded field effect transistors
702
-
1
through
702
-
8
. The drains of the source-grounded transistors
701
-
1
through
701
-
8
are respectively connected to the sources of the corresponding gate-grounded transistors
702
-
1
through
702
-
8
. Amplifying circuits that combine source-grounded amplifying transistors and gate-grounded amplifying transistors are called “cascode amplifying circuits”. In the example shown in
FIG. 7
, eight cascode amplifying circuits are provided. Specifically, this distributed amplifier
700
has an eight-section construction.
The sources of the source-grounded transistors
701
-
1
through
701
-
8
are connected in common to a ground line. Furthermore, the gates of the gate-grounded transistors
702
-
1
through
702
-
8
are connected in common to a VC power supply.
The gates of the gate-grounded transistors
701
-
1
through
701
-
8
are connected to a signal input terminal
711
. A signal IN is input from the signal input terminal
711
.
The drains of the gate-grounded transistors
702
-
1
through
702
-
8
are connected to a signal output terminal
712
. A signal OUT is output from the signal output terminal
712
. A power supply potential VDD is applied to this signal output terminal
712
by means of an external bias circuit not shown in the figures.
Coplanar transmission lines
703
-
1
through
703
-
8
,
704
-
1
through
704
-
8
,
705
-
1
through
705
-
8
and
706
-
1
through
706
-
8
are used as transmission paths that are connected between the source-grounded transistors
701
-
1
through
701
-
8
and the gate-grounded transistors
702
-
1
through
702
-
8
.
The transmission line consisting of the coplanar transmission lines
703
-
1
through
703
-
8
is connected to a ground line via a terminating resistance
707
and a capacitor
708
. A bias input terminal
713
is connected between the terminating resistance
707
and capacitor
708
. The bias input terminal
713
is used for the external connection of another capacitor in cases where the capacitance of the capacitor
708
in insufficiently large; furthermore, this bias input terminal
713
is also used to supply the gate bias TMI of the source-grounded transistors
701
-
1
through
701
-
8
. Here, when the gate bias TMI is supplied, an external circuit (not shown in the figures) must be connected to the bias input terminal
713
in order to cut the direct-current component.
The transmission line consisting of the coplanar transmission lines
706
-
1
through
706
-
8
is connected to a ground line via a terminating resistance
709
and a capacitor
710
. A terminal
714
is connected between the terminating resistance
709
and the capacitor
710
. This terminal is used for the external connection of another capacitor in cases where the capacitance of the capacitor
710
in insufficiently large. Here, a terminating resistance (not shown in the figures) is externally connected to the signal output terminal
712
. Specifically, in this distributed amplifier
700
, two output side terminating resistances are used. These output side terminating resistances are connected in parallel as seen from the side of the gate-grounded transistors
702
-
1
through
702
-
8
.
The circuit thus constructed can be caused to function as a broadband amplifier by appropriately setting the potentials VDD, VC and TMI. The voltage gain Gv of this distributed amplifier is given by Equation (1) below. In Equation (1), n is the section number, and gm is the mutual conductance per section. Furthermore, RL/2 is the synthesized value of the two output side terminating resistances.
Gv=
n×gm×RL/
2  (1)
Ordinarily, the voltage gain Gv of the distributed amplifier is set by varying the potential TMI, i.e., the gate bias of the source-grounded transistors
701
-
1
through
701
-
8
. Varying the potential TMI causes that voltages across the gates and sources of the respective source-grounded transistors
701
-
1
through
701
-
8
to vary; as a result, the mutual conductance gm varies, so that the voltage gain Gv can be varied. In cases where the potential TMI is used, the voltage gain Gv can be continuously varied from zero to the maximum value Gvmax.
However, the distributed amplifier shown in
FIG. 7
suffers from the following drawback: specifically, when the potential TMI is varied in order to reduce the voltage gain Gv, there is also a variation in the output signal waveform. Such waveform variation is usually a problem for the device that receives such an output signal. The effect of this drawback is especially conspicuous in the case of distributed amplifiers used to amplify base-band digital signals used in optical communications devices and the like.
FIGS. 8A-8D
show simulated results for the input waveform and output waveform of the distributed amplifier
700
. In this simulation, GaAs Pseudomorphic HEMTs (high electron mobility transistors) with a gate length of 0.1 m and a gate width of 40 m were used as the respective transistors
701
-
1
through
701
-
8
and
702
-
1
through
702
-
8
.
FIG. 8A
shows the waveform of the input signal IN (see FIG.
7
). The input signal IN is a 40 Gbps seven-stage quasi-random signal with an amplitude of 0.5 volts (i.e., 0.5 Vpp). A waveform of the type shown in
FIG. 8A
is called an eye pattern. When a waveform is evaluated using an eye pattern, the position of the cross point between the rising portion and falling portion of the signal is an important parameter. Specifically, it may be said that the deterioration of the signal waveform becomes more severe as the positional deviation of the cross point increases. In most cases, as is shown in
FIG. 8A
the cross point of the input signal IN is set so that this cross point is positioned substantial center between the high level and the low level.
FIG. 8B
shows the waveform of the output signal OUT that was obtained when the potential TMI was set at zero volts. The voltage gain Gv in this case was 3.4. As is seen from
FIG. 8B
, the position of the cross point of the output signal OUT, like that of the cross point of the input signal IN (see
FIG. 8A
) is more or less the center between the high level and low level.
FIG. 8C
shows the waveform of the output signal OUT that was obtained when the potential TMI was set at −0.25 volts. The voltage gain Gv in this case was 3.2. As is seen from
FIG. 8C
, the position of the cross point of the output signal OUT is slightly higher than the positions of the cross point in the waveforms shown in FIGS.
8
(A) and
8
(B).
FIG. 8D
shows the waveform of the output signal OUT that was obtained when the potential TMI was set at −0.50 volts. The voltage gain Gv in this case was 2.2. As is seen from
FIG. 8D
, the position of the cross point of the output signal OUT is more higher than the position of the cross point in the waveform shown in FIG.
8
C.
The reasons for such deviation of the cross point will be described below with reference to FIG.
9
.
FIG. 9
is a graph which shows the relationship between the gate-source voltage Vgs and the mutual conductance gm in the source-grounded transistors
701
-
1
through
701
-
8
. In
FIG

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