Distributed access serial port test arrangement for integrated c

Details Distributed access serial port test arrangement for integrated c Distributed access serial port test arrangement for integrated c

1988-09-08

1989-08-29

Karlsen, Ernest F.

Electricity: measuring and testing

Plural, automatically sequential tests

371 25, G01R 3128

Patent

active

048620726

ABSTRACT:
A dedicated set of four input pads or pins of an LSI chip provides access by a serial data line to macrocells or other partioned logic of the LSI for individual test. A macrocell is connected to the remainder of the logic by a pair of multiplexer/test register combinations, one at the input, and one at the output of the macrocell. In a normal operation mode, the multiplexers connect each macrocell to the next, for normal signal flow. Under control of test signals, the test registers may be selectively loaded with data from the serial data bus, and the multiplexers may be switched to apply test data from the test register to a macrocell. The output multiplexer of the macrocell routes the resulting processed test data to the output test register, so it may be read out in serial form while normal operation resumes.

REFERENCES:
patent: 4710931 (1987-12-01), Bellay et al.
patent: 4710933 (1987-12-01), Powell et al.
patent: 4754215 (1988-06-01), Kawai
patent: 4760335 (1988-07-01), Lindberg
patent: 4791358 (1988-12-01), Sauerwald et al.

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