Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Encapsulating
Reexamination Certificate
1998-05-18
2002-04-16
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Encapsulating
C438S126000, C257S787000, C174S050510, C361S748000
Reexamination Certificate
active
06372553
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to encapsulation of substrate based electronic packages using injection molding with a two piece mold and more particularly to the use of a barrier material formed over the gating area of the substrate which is later peeled away and discarded.
(2) Description of the Related Art
Injection molding using a two piece mold is often used for encapsulation of electronic devices. This requires the formation of-a gating area on the substrate surface for removal of the mold runner after the encapsulation is complete and the encapsulant is cured. The gating area usually has a metal formed on the substrate such as palladium or gold. This places severe restrictions on the routing of circuit traces formed on the surface of the substrate.
U.S. Pat. No. 5,635,671 to Freyman et al. describes a degating region having a material formed thereon chosen such that the material in the degating region forms a weak bond with the encapsulant used. Freyman et al. describe the used of degating material such as gold so that wiring traces must be routed away from the degating region.
U.S. Pat. No. 5,311,402 to Kobayashi et al. describes an integrated circuit chip bonded to a circuit board with a cap for hermetically sealing the chip. The cap is bonded to the circuit board at the edges of an open end thereof and bonded to the underside or bottom of the chip.
U.S. Pat. No. 5,099,101 to Millerick et al. describes an automatic laser trimming apparatus for semiconductor integrated chip packages which performs deflashing and degating operations.
U.S. Pat. No. 4,954,308 to Yabe et al. describes a resin encapsulating method using upper and lower half molds.
SUMMARY OF THE INVENTION
Electronic circuit packages typically comprise a substrate with one or more integrated circuit elements attached. Molded packages are often used for the encapsulation of the integrated circuit element because they provide a reliable encapsulation at a reasonable cost.
FIG. 1
shows a cross section view of such a package. The package has a substrate
10
with an integrated circuit element
12
attached to the first surface
26
of the substrate
10
. Circuit traces
18
on the first surface
26
of the substrate communicate with circuit traces
22
on the second surface
27
of the substrate using via connections
20
through the substrate. Input/output balls
24
provide ball grid array type input/output connections for the package. The input/output balls can be a material such as solder, solder coated copper, or the like. The connections between the integrated circuit element
12
and the circuit traces
18
on the first surface
26
of the substrate
10
are provided by wire bonds
16
.
The substrate based package is encapsulated with a molded encapsulant
14
. In most cases the molded encapsulant
14
is a molded plastic. In packages of this type the molded encapsulant is usually formed using an injection molding process using a two piece mold. The two piece mold is preferred because of cost, but requires a gate region on the substrate as will be explained with reference to
FIGS. 2-5
.
A cross section of a part of a two piece mold is shown in FIG.
2
. The mold has an upper part
30
, a lower part
28
, a cavity
34
in the upper part
30
of the mold and a recess
29
in the lower part
28
of the mold. The substrate
10
with the integrated circuit element
26
attached fits into the recess
29
of the lower part
28
of the mold. As can be seen in
FIG. 2
, the input/output balls have not been formed on the substrate at this point in the processing. A mold runner channel
32
is formed in the upper part of the mold
30
and forms a path for the uncured encapsulant to flow into the cavity
34
in the upper part
30
of the mold.
FIG. 3
is a plan view of the upper part
30
of the mold, taken along line
3
-
3
′ of
FIG. 2
, showing the cavity
34
and the mold runner channel
32
.
During the encapsulation process uncured encapsulant is forced to flow from a source, not shown, through the mold runner channel
32
into the cavity
34
, thereby filling the cavity. When the encapsulant is cured, encapsulant in the mold runner channel is also cured forming a mold runner
33
, as shown in FIG.
4
. This mold runner
33
must be removed after the encapsulant has cured. To accomplish the removal of the mold runner
33
a degating region
36
is typically formed on the first surface
26
of the substrate
10
at the substrate location which will be directly under the mold runner channel
32
, see
FIGS. 2 and 4
. The degating region is formed of a material chosen such that the adhesive force between the encapsulant and the degating region material is less than the adhesive force between the encapsulant and the substrate. The degating region material is usually a metal such as gold or palladium.
With degating regions formed in this manner the circuit traces
18
on the first surface of the substrate and vias
20
between the first surface and second surface of the substrate must be routed to avoid the degating region
36
, as shown in FIG.
5
. The dashed lines in
FIG. 5
show the location of the mold runner channel
32
and the perimeter
35
of the cavity. Degating regions of this type consume valuable surface area on the first surface of the substrate which could be used for circuit traces of vias. In addition mold compound material normally will flash outside the degating region and can cause problems.
It is a principle objective of this invention to provide a method of encapsulation of substrate based electronic devices using a gating region on a substrate which can be formed directly over circuit tracing.
It is another principle objective of this invention to provide a substrate, for substrate based electronic devices, wherein the substrate uses a gating region on a substrate which can be formed directly over circuit tracing.
These objectives are achieved by attaching a barrier material to the region of the substrate where the mold runner channel will be located when the package is encapsulated. The barrier material can be attached directly over circuit traces or via holes. The barrier material is chosen such that the adhesive force between the barrier material and the adhesive is less than the adhesive force of the cured encapsulant to the barrier material. After the encapsulation has been completed and the encapsulant cured the mold runner is removed thereby also removing the barrier material.
REFERENCES:
patent: 5467252 (1995-11-01), Nomi et al.
patent: 5635671 (1997-06-01), Freyman et al.
patent: 5852870 (1998-12-01), Freyman et al.
patent: 5961912 (1999-10-01), Huang et al.
patent: 5969427 (1999-10-01), Wensel
patent: 5981873 (1999-11-01), Heo
patent: 5982625 (1999-11-01), Chen et al.
Ackerman Stephen B.
Prescott Larry J.
Saile George O.
ST Assembly Test Services PTE LTD
Wilczewski Mary
LandOfFree
Disposable mold runner gate for substrate based electronic... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Disposable mold runner gate for substrate based electronic..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Disposable mold runner gate for substrate based electronic... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2847255