Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-03-15
2004-10-26
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C315S169400
Reexamination Certificate
active
06809707
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a method of displaying an interlaced video signal with frames of a first and a second video field on a matrix display panel which is sub-field and interlaced driven. The invention further relates to a circuit for displaying an interlaced video signal on a sub-field and interlaced driven matrix display panel. The invention also relates to a matrix display device comprising such a matrix display panel.
An interlaced video signal has a frame period with a first and a second video field period. Usually, the odd lines of the video signal form the first video field, and the even lines of the video signal form the second video field. When this interlaced video signal has to be displayed on the ALIS PDP, the odd lines of the video signal are displayed on the odd display lines, and the even lines of the video signal are displayed on the even display lines. Usually interlaced video signals have field rates of 50 Hz or 60 Hz, and thus frame rates of 25 Hz or 30 Hz, respectively, which gives rise to line flicker.
SUMMARY OF THE INVENTION
It is, inter alia, an object of the invention to reduce the line flicker.
To this end, a first aspect of the invention provides a method of displaying an interlaced video signal with frames of a first and a second video field on a matrix display panel which is sub-field and interlaced driven as claimed in claim
1
. A second aspect of the invention provides a circuit for displaying an interlaced video signal on a sub-field and interlaced driven matrix display panel as claimed in claim
4
. A third aspect of the invention provides a matrix display device comprising such a matrix display panel and such a circuit as claimed in claim
5
. Advantageous embodiments are defined in the dependent claims.
In the prior art, each video field of the interlaced video signal is displayed on the corresponding display field during a video field period. It is known to generate the gray scales of the displayed video by driving the PDP in a sub-field mode. During each display field a number of sub-fields is generated, each sub-field comprising a prime period and a sustain period. During the prime period, a select driver selects the display lines (rows) one by one to prime the display cells of the selected row with data signals. The data signals are supplied in parallel by a data driver which receives the video signal Vs. During the sustain period, the select driver supplies pulses to all the rows associated with the active display field. The plasma channels are ignited a predetermined number of times to generate light from the pixels primed to do so. The amount of light produced depends on the number of ignitions. Sustain periods with a different number of ignitions are associated with the different sub-fields in a display field period. The amount of light generated during a display field is the sum of the different amounts of light produced during the sub-fields of this display field. The PDP is able to produce gray scales because, during the priming period of each sub-field, it is possible to select whether a certain pixel has to produce light during the subsequent sustain period or not. Each sub-field or each display field comprises an erase period. During the erase period, all pixels associated with the display field are erased. Detailed information on the sub-field operation of a PDP can be found in EP-B-0549275, which is herein incorporated by reference.
In accordance with the invention, at least a first and a second display period are generated during the frame period of the video signal. During each display period, the first and the second display field are alternately selected for displaying information related to the first and the second video field, respectively. The sub-field weights associated with the first and the second display fields of the first display period differ by at least one weight from the sub-field weights associated with the first and the second display field of the second display period. Thus, within one video frame period, the amount of light produced with respect to the video signal occurring during one video field period is now spread across at least two display fields which are separated by a display field with which another video field is associated. Consequently, the repetition frequency of light pulses associated with one video field increases and line flicker is reduced.
The sub-field weights associated with a first and a second display field of a certain display period may differ. The sub-field weights associated with different first or second display fields in a certain video frame period may be partly the same.
In an embodiment of the invention, two display periods or four display fields occur within one video frame period. During these four display fields, sub-fields are generated which are alternately associated with video information of a first and a second video field, respectively.
In the prior art, eight sub-fields with different binary weights are used to obtain 256 gray levels per color. The following example elucidates this embodiment of the invention by defining the sub-fields generated during one video frame period with four display fields. During the first display field, the video signal of the first video field is displayed by generating six sub-fields with the least significant weights. During the second display field, the video signal of the second video field is displayed by again generating six sub-fields with the least significant weights. During the third display field, the video signal of the first video field is displayed by generating six sub-fields with the most significant weights. During the fourth display field, the video signal of the second video field is displayed by generating six sub-fields with the most significant weights.
In an embodiment of the invention, the sub-field weights associated with the first display fields in a video frame period are substantially evenly distributed across all first display fields. As an example, four display fields are generated during one video frame period, a total of eight binary weighted sub-fields is associated with one video field, and four sub-fields occur during each display field. The weights of the eight sub-fields are
1
,
2
,
4
, . . . ,
128
. As a first example, the weights
1
,
4
,
16
,
64
are associated with the first and the second display field, and the weights
2
,
8
,
32
,
128
are associated with the third and the fourth display field. As a second example, the weights
1
,
2
,
4
,
128
are associated with the first and the second display field, and the weights
8
,
16
,
32
,
64
are associated with the third and the fourth display field.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.
REFERENCES:
patent: 5436634 (1995-07-01), Kanazawa
patent: 5912651 (1999-06-01), Bitzakidis et al.
patent: 6034482 (2000-03-01), Kanazawa et al.
patent: 6097357 (2000-08-01), Shinoda et al.
patent: 6104362 (2000-08-01), Kuriyama et al.
patent: 6337674 (2002-01-01), Kim
patent: 6424325 (2002-07-01), Van Dijk
patent: 0549275 (1993-06-01), None
patent: 8123355 (1996-05-01), None
Koninklijke Philips Electronics , N.V.
Said Mansour M.
Shalwala Bipin
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