Computer graphics processing and selective visual display system – Display driving control circuitry – Physically integral with display elements
Reexamination Certificate
1995-06-02
2001-08-28
Chang, Kent (Department: 2673)
Computer graphics processing and selective visual display system
Display driving control circuitry
Physically integral with display elements
C345S098000, C345S204000
Reexamination Certificate
active
06281891
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to circuitry for driving data lines of an array formed on a substrate.
Matsueda, Y., Ashizawa, M., Aruga, S., Ohshima, H., and Morozumi, S., “Defect-Free Active-Matrix LCD with Redundant Poly-Si TFT Circuit,”
SID
89
Digest
, Vol. XX, 1989, pp. 238-241, describe a liquid crystal display (LCD) in which an active matrix includes scanning lines and data lines formed on a substrate. As shown in
FIG. 1
, Y-drivers for the scan lines are formed on the same substrate, along two opposite sides of the active matrix. X-drivers for the data lines are also formed on the same substrate, along the other two sides of the active matrix. As described at page 238 in relation to
FIG. 1
, the X-drivers can include two shift registers, 16 video lines, and a 1280 TFT array controlled by the shift registers. Each video line can be divided into eight parallel lines to provide a data input frequency at which TFT circuits can operate. As shown in
FIG. 1
, each of the parallel lines is connected to a TFT of every eighth data line.
Lee, S. N., Stewart, R. G., Ipri, A., Jose, D., and Lipp, S., “FAM 13.5: A 5×9 Inch Polysilicon Gray-Scale Color Head Down Display Chip,” 1990
IEEE International Solid-State Circuits Conference Digest of Technical Papers,
1990, pp. 220-221 and 301, describe a display in which scanning electronics can be integrated onto a glass plate along with pixel switching transistors. Both data-line and select-line driver circuits can be fabricated on a glass substrate along with polysilicon thin-film transistors. As shown and described in relation to
FIG. 2
, fully-redundant data scanners are at the top of array and select scanners are on left and right. As shown and described in relation to
FIG. 3
, gray-scale data scanners partitioned into registers driven from a bus have 25 leads connected to the inputs of four 20-stage shift registers that are driven by four external clocks separated by 90 degrees. A chop ramp scanning technique can handle the 32 gray levels color display requirement, with each data line driven by a transmission gate controlled by the output of a 5-bit counter. As shown and described in relation to
FIG. 4
, a five-bit gray scale counter is associated with the data scanner circuitry. During a first line period, a 5-bit gray scale code for each pixel is loaded into the data shift registers. At the end of the line period, the data is transferred from the shift register latches to the counters. During a second line period, a master data bus is ramped by a low impedance driver from 0V to 5V, as shown in
FIGS. 6
a
and
6
b
. The master data line ramp is always the same and does not contain any image information. The analog information presented to the data lines depends entirely on the contents of their counters. The counter clock increments all data line counters, and whenever each counter reaches a count of 11111, it sets the control-latch flip-flop to turn off the transmission gate. This chop ramp scanning circuit can achieve accurate, uniform 32 step digital-to-analog conversion, and integration of the scanning circuitry can reduce the number of input leads. The data line driving circuitry includes only one analog input line, referred to as a ramp line. The ramp line provides a ramp signal to a channel lead of every transfer gate TFT. For each data line's TFT, a counter is connected between the shift register and the TFTs gate to ensure that each data line receives only its signal.
FIG. 8
shows timing for the circuitry in
FIG. 3
, showing the RAMP line as an analog signal.
FIG. 9
shows a chop ramp technique for gray scale conversion.
Lewis, EP-A 0 540 163, describes switched capacitor analog circuits constructed from polysilicon (poly-Si) TFTs and thin film capacitors (TFCs). The circuits can be fabricated on large area substrates and integrated with, for example, flat panel displays, pagewidth optical scan arrays, or pagewidth printheads. The analog switched capacitor circuits can be used to form data drivers, including sampling amplifiers and digital-to-analog converters (DACs) for AMLCDs. As shown and described in relation to
FIGS. 5-9
, switched capacitor amplifiers settle with cycle times well below 60 &mgr;s, the approximate line time available for a conventional TV resolution AMLCD; in addition, the amplifiers respond with good linearity and without clipping. As shown and described in relation to
FIGS. 10-13B
, all thin-film charge redistribution DACs can be constructed for AMLCD data driving or other applications. As shown and described in relation to
FIGS. 14A and 14B
, an array of video sampling amplifiers with polysilicon TFT components can be used to drive the data lines of an AMLCD. As shown and described in relation to
FIGS. 15A and 15B
, a display driver architecture can use DACs implemented entirely in TFTs and TFCs, with a multiplexer at the output of each DAC, allowing each DAC to drive several lines by switching the DAC output between the data lines.
SUMMARY OF THE INVENTION
The invention addresses problems that arise in providing data drive signals to an active matrix array of circuitry formed on a substrate.
A two-dimensional (2D) array, for example, can include two sets of conductive lines extending in perpendicular directions. Each line extending in one direction can provide signals to a column of the array; each line extending in another direction can provide signals to a row of the array.
Conventionally, each row-column position in a 2D array includes circuitry, sometimes called a “cell,” that responds to signals on the lines for the cell's row and column combination. Through one set of parallel lines, illustratively called “data lines,” each cell receives signals that determine its state. Through the other set of parallel lines, illustratively called “scan lines,” each cell along a scan line receives a signal that enables the cell to receive signals from its data line.
In conventional arrays, each scan line provides a periodic scan signal that enables a component in each cell connected to the scan line to receive a signal from its data line during a brief time interval of each cycle. Therefore, tight synchronization of the scan signals with signals on the data lines is critical to successful array operation. Tight synchronization in turn requires that the driving signals to the data lines be provided with precise timing.
One way to obtain precisely timed data drive signals is to provide an external input lead for each data line. Groups of external input leads can then be connected by tape automated bonding (TAB) to circuitry that is external to the substrate. For example, the external circuitry can include, for each data line, a DAC implemented in single crystal circuitry. This approach requires a large number of TAB connections, however, and fails whenever one of the TAB connections fails mechanically. In addition, the large number of TAB connections precludes a small, high performance display such as a projection display.
The above-described article by Matsueda et al. exemplifies another approach that is used in conventional poly-Si TFT AMLCDs. In this approach, each of m analog input lines provides a data drive signal to every mth data line, and the data drive signals are sampled under control of a shift register that is integrated on the substrate. In this shift register sampling approach, each analog input line has an external input lead for receiving a data drive signal from one of m DACs on a board external to the substrate. The analog input lines and the shift register input leads are connected to a driver board through a flex connector.
The shift register sampling approach is problematic, however, because the time available for charging a data line is short, so that accurate voltage sampling is difficult, precluding accurate gray scale rendition. In addition, the clock rate required for the shift register can be very high. These problems become worse as the display pixel count increases.
The problems with shift register sampling can be allev
DaCosta Victor M.
Lewis Alan G.
Chang Kent
Xerox Corporation
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