Computer graphics processing and selective visual display system – Computer graphic processing system – Integrated circuit
Reexamination Certificate
1998-06-01
2001-04-10
Chauhan, Ulka J. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphic processing system
Integrated circuit
C345S519000, C711S200000
Reexamination Certificate
active
06215507
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to computer generated displays and in particular to an improved display memory controller.
Within the architecture of many personal computers, graphics and video data are stored in a display memory. The interface to this display memory is through a memory controller often contained within a graphics/video controller subsystem.
Typically, there are at least four devices in the computer system that can access the display memory. These devices are the CRT controller, real time video controller, bitBLT engine, and system logic (CPU) interface. The CRT controller reads data out of display memory and supplies it to a monitor interface to be displayed on the monitor such as a CRT or LCD display. The real time video controller collects streaming video data from an external video source and writes it to display memory. The bit block transfer (bitBLT) engine controls the movement of rectangular blocks of data from one area of display memory to another. The system logic (CPU) interface passes along display memory read and write requests from the host CPU.
A computer graphics monitor is, by nature, a two-dimensional pixel-oriented device, whereas the display memory is, by nature, a linear, byte-oriented device. In a linear memory, the byte(s) of data which defines the nature of the display that is to be generated at a particular pixel location is located at a specific location within the memory and is located by a single address rather than by two or more coordinates. When the display memory is to be accessed, the x and y coordinates of the pixel that needs to be read or written must be provided. Within the memory controller a translation must occur from the x,y pixel coordinate to the linear display memory address where the data for the pixel is stored. This display memory address may be expressed in the form of an “offset”, that is the distance between the actual address of the data for the pixel and the initial address in the display memory at which the display data begins. Currently, within common personal computer architectures, the display memory address of a pixel at coordinate x & y is calculated by multiplying the number of pixels per line of the display raster (pitch) by the “y” coordinate of the pixel location, then adding the “x” value of the pixel location. Within the memory itself, the data for the pixels are stored in raster order starting with the data for the pixel at the top left corner and ending with the data for the pixel in the bottom right corner. The actual address offset in display memory will depend upon the color depth that is being used to store the graphics data (e.g. 4 bits-per-pixel (bpp), 8 bpp, 16 bpp, 24 bpp, 32 bpp, etc.) By way of example, in a computer display with 640 pixels in the “x” direction and 480 pixels in the “y” direction (e.g. 640×480 screen resolution), consider a pixel at coordinate x=240, y=160. The address (offset) of the data for this pixel would be (160×640)+240=102,640 (decimal).
The translation in the memory controller from the x,y pixel address to the corresponding offset in display memory requires a “multiplier” and an “adder”. Such devices are costly in terms of required die area on an integrated circuit. It is desirable, therefore, to have an alternative method and apparatus for performing the translation, but one which dispenses with the multiplier/adder requirement.
SUMMARY OF THE INVENTION
The above and other needs are met by eliminating the multiplier and adder required by the typical current implementations and creating the display memory offset address by interleaving the pixel x-coordinate and pixel y-coordinate bits.
More specifically, in the preferred embodiment, the computer display is divided conceptually into 32 pixel by 32 pixel blocks (tiles). In the case of a 640 pixel by 480 pixel screen resolution, 640 pixels in the x direction is equivalent to twenty tiles and 480 pixels in the y direction is equivalent to fifteen tiles. Within each tile, the offset for a given pixel location in that tile from the initial address for that tile is given by using a bit-by-bit interleaving of x and y coordinates for that pixel as follows: y
4
y
3
x
4
x
3
y
2
x
2
y
1
y
0
x
1
x
0
. The offset for the pixel data is much more readily generated in this manner than is the case with existing approaches using a multiplier and adder.
The use of this improved addressing method, however, requires a rearrangement of the pixel data in the display memory. In conventional structures it is common to store the data for all the pixels of a scan line in contiguous memory locations, followed by the data for all the pixels of the next succeeding scan line, etc. As will be better understood from the following detailed description, in the preferred embodiment of the invention, data for the first four pixels of a scan line are stored in contiguous locations, followed by data for the first four pixels of the next scan line. The specifics of this “zig-zag” ordering within a tile is a function of the order in which the bits of the pixel x and y coordinates are interleaved. Suffice to say that all the data for the pixels of a given tile is stored in contiguous locations of the display memory. The particular bit interleave order in this embodiment was carefully chosen to optimize the storage of graphics data in memory. Other interleave orders are, of course, within the contemplation of this invention.
The page size of many DRAMs is 1024 bytes. For a pixel depth of eight bpp, each tile would require one DRAM page. Likewise, for pixel depths of sixteen bpp, 24 bpp, and 32 bpp, each tile would require two, three and four DRAM pages respectively. Therefore, a 32 by 32 tile will always be DRAM page-aligned, regardless of the color resolution used. This simplifies management of the memory.
The offset for a given tile is developed by interleaving the higher order bits of the x and y locations for any pixel located within that tile. This interleaving is as follows: x
10
y
9
y
8
x
9
x
8
y
7
x
7
y
6
x
6
y
5
x
5
. This is to be distinguished from the interleaving using the lower order bits. The address using the lower order bits gives the offset of the data for a given pixel from the beginning address of its tile, and where the units of the measurement are memory locations. In the case of the offset using the higher order bits, the offset is given from the initial location of the display data in the display memory, but the units of the offset are the number of tiles preceding the given tile in memory.
Finally, the offset for the data for a given pixel, in units of memory locations from the initial location of the display data in the display memory and in units of memory locations is given by concatenating the addresses from the lower order and higher order bits of a particular pixel location as follows:
x
10
y
9
y
8
x
9
x
8
y
7
x
7
y
6
x
6
y
5
x
5
y
4
y
3
x
4
x
3
y
2
x
2
y
1
y
0
x
1
x
0
.
It should also be noted that, due to the zig-zag ordering of the pixel data within the files, memory is partitioned into 4×4 and 8×8 sub-tiles. This organization is ideal for 3D graphics where everything (displayable objects, characters, etc.) is broken down into 2D triangles and rendered onto the display as groups of triangles. These are very intense 2D operations and the x,y ordering of memory used in the practice of this invention actually improves the efficiency and performance of the graphics engine.
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Nally Robert Marshall
Nelsen Pete Edward
Brady III W. James
Chauhan Ulka J.
Laws Gerald E.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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