Display refresh system having reduced memory bandwidth

Details Display refresh system having reduced memory bandwidth Display refresh system having reduced memory bandwidth

1995-06-07

1997-09-23

Hjerpe, Richard

Computer graphics processing and selective visual display system

Display peripheral interface input device

Light pen for fluid matrix display panel

345200, G09G 536

Patent

active

056709935

ABSTRACT:
A display refresh system (10) is disclosed wherein a display image is stored in a screen memory (12) as a number of screen rows (26) having consecutive addressable units. A redundancy memory (38) includes a redundancy row (48) corresponding to each screen row (26). Each redundancy row (48) stores run length data that indicates the number of identical consecutive addressable units within a screen row (26). Addressable units are written with accompanying run lengths to a FIFO (54). A register repeater (56) repeats the addressable unit at the FIFO output (62) a number of times equal to the run length. The run length is used to advance the refresh address to the next group of identical consecutive addressable units within the screen row (26).

REFERENCES:
patent: 4233601 (1980-11-01), Hankins et al.
patent: 4799053 (1989-01-01), Van Aken et al.
patent: 4827253 (1989-05-01), Maltz

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