Display refresh memory with variable line start addressing

Details Display refresh memory with variable line start addressing Display refresh memory with variable line start addressing

1980-11-20

1983-01-11

Trafton, David L.

Communications: electrical

Land vehicle alarms or indicators

Internal alarm or indicator responsive to a condition of the...

340750, 364900, G09G 116

Patent

active

043684661

ABSTRACT:
A display refresh system wherein a RAM refresh buffer is tightly packed. Line start addresses in the buffer are determined by the line length such as eighty characters. With each of the lines in the refresh buffer being normally a binary number such as 128 characters in length the line start addresses are such that they do not coincide with the beginning of each line in the buffer. To assure packing they are interspersed each 80 positions sequentially within the buffer. A processor loads the address of each line start character into the pointer area of the refresh buffer. A line counter is used which counts the lines being displayed on the display. The RAM refresh buffer which contains the line start addresses and character data is first addressed by the line counter output to provide the line address. Since the refresh buffer is used as the line pointer register the output bus for pointer data and character data is common. Once the address of the first character in a line is read from the pointer area in the refresh buffer it is loaded into the refresh buffer address counter which then controls the sequential reading of characters in that line from the refresh buffer onto the data bus. Following the reading of each line the sequence is repeated, e.g., the line counter is incremented, its' count used to address the pointer register and the address contained in the pointer register loaded into the refresh buffer address counter.

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patent: 4117469 (1978-09-01), Levine
patent: 4129858 (1978-12-01), Hara
patent: 4203107 (1980-05-01), Lovercheck
patent: 4249172 (1981-02-01), Watkins et al.
D. M. Neal & H. C. Tanner; "Linking Algorithm for Display Memory;" I.B.M. Tech. Discl Bul., vol. 21, No. 11, Apr. 1979, pp. 4330-4331.
H. C. Tanner; "Linking Algorithm with Segmentation;" I.B.M. Tech. Discl. Bul., vol. 21, No. 11, Apr. 1979, pp. 4332-4333.

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