Display panel with integral memory capability for each display e

Details Display panel with integral memory capability for each display e Display panel with integral memory capability for each display e

1977-03-23

1978-09-05

Smith, Alfred E.

Electric lamp and discharge devices: systems

Plural power supplies

Plural cathode and/or anode load device

340324M, 340166EL, 315169R, H05B 3700, H05B 3900, H05B 4100

Patent

active

041123336

ABSTRACT:
A planar display panel is described having an X-Y array of individually controllable display elements. A thin film floating gate transistor with memory capability is disposed integral with each display element. A storable information potential is applied to the transistor gate to induce a potential on the floating gate which determines high and low conductance states for the transistor. Preferred operating modes are set forth. A preferred physical layout for the display elements is provided in which the memory transistor is optimally located to provide the maximum display area.

REFERENCES:
patent: 3840695 (1974-10-01), Fischer
patent: 3885196 (1975-05-01), Fischer
patent: 4041481 (1977-08-01), Sato
patent: 4042854 (1977-08-01), Luo et al.
"Human Performance Evaluation of Matrix Displays . . .", Report No. Ad/A-029932, pp. 124-130.
"Experimental Realization of Floating-Gate-Memory Thin-Film Transistor", Yu, Brody, & Chen, Proceedings of the IEEE, May 1975, pp. 826, 827.

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