Computer graphics processing and selective visual display system – Display driving control circuitry – Display power source
Reexamination Certificate
1999-06-03
2001-12-25
Lao, Lun-Yi (Department: 2673)
Computer graphics processing and selective visual display system
Display driving control circuitry
Display power source
C345S211000, C345S060000, C345S076000, C345S087000, C315S169300, C315S169400
Reexamination Certificate
active
06333738
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a driving apparatus of a display panel having a capacitive load, such as a plasma display panel of an AC driving type (hereinafter, called PDP), an electro-luminescence display (hereinafter, called EL), or the like.
2. Description of Related Art
Display apparatuses that use a flat panel of a self light emission type such as PDP, EL, or the like, are commercially available as wall type TV sets.
FIG. 1
is a schematic diagram which shows the structure of a display apparatus of that type.
As
FIG. 1
shows, a PDP
10
provided as a display panel comprises two sets of row electrodes Y
1
to Y
n
and X
1
to X
n
. Two electrodes from each of these electrode sets together constitute a row electrode pair (X, Y) that corresponds to each row (the first row to the nth row) of one picture plane. In the PDP
10
, column electrodes Z
1
to Z
m
, which are arranged perpendicularly to the row electrode pairs are further provided so that the row electrodes and the column electrodes sandwich a dielectric layer and a discharge space which are not particularly shown in the figure. Each of the column electrodes Z
1
to Z
m
respectively corresponds to each column (the first column to the mth column) of one picture plane. One discharge cell C
(i, j)
is formed in an intersecting portion between a row electrode pair (X, Y) and a column electrode Z.
The display apparatus includes a pair of row electrode driving circuits
30
and
40
.
At first, the row electrode driving circuit
30
generates a reset pulse RP
y
of a positive voltage as shown in
FIGS. 2C
to
2
F and applies it to the row electrodes Y
1
, to Y
n
, simultaneously. At the same time, the row electrode driving circuit
40
generates a reset pulse RP
x
of a negative voltage as shown in
FIG. 2B
, and simultaneously applies it to all of the row electrodes X
1
to X
n
.
By applying the reset pulses RP
x
, and RP
y
simultaneously, all of the discharge cells of the PDP
10
are excited to discharge and charged particles are generated. After the discharge is terminated, a predetermined amount of wall charges are uniformly formed in the dielectric layer of all of the discharge cells (resetting stage).
After the completion of the resetting stage, a column electrode driving circuit
20
of the display apparatus generates pixel data pulses DP
1
to DP
n
according to pixel data corresponding to the first row to the nth row of the picture plane and sequentially applies them to the column electrodes Z
1
to Z
m
as shown in FIG.
2
A. The row electrode driving circuit
30
generates a scanning pulse SP of a negative voltage in accordance with the timing of the application of the pixel data pulses DP
1
to DP
n
and sequentially applies it to the row electrodes Y
1
to Y
n
, as shown in
FIGS. 2C
to
2
F.
Among the discharge cells that belong to the row electrodes to which the scanning pulse SP has been applied, a discharge occurs in those discharge cells to which the pixel data pulse of the positive voltage has been simultaneously applied. As a result the discharge, most of the wall charges are extinguished. Conversely, no discharge occurs in those discharge cells to which the scanning pulse SP has been applied but the pixel data pulse of the positive voltage is not applied. The wall charges remain unchanged in those discharge cells. In this way, the discharge cell in which the wall charges remain becomes a light-emission discharge cell and the discharge cell in which the wall charges have been extinguished becomes a non-light emission discharge cell (addressing stage).
After the addressing stage has finished, the row electrode driving circuits
30
and
40
continuously apply a sustaining pulse IP
y
of the positive voltage to each of the row electrodes Y
1
to Y
n
as shown in
FIGS. 2C
to
2
F. The row electrode driving circuits
30
and
40
also continuously apply a sustaining pulse IP
x
of the positive voltage to each of the row electrodes X
1
to X
n
at a timing deviated from the timing of the application of the sustaining pulse IP
y
, as shown in FIG.
2
B.
For a period of time during which the sustaining pulses IP
x
and IP
y
are alternately applied, the discharge light emission is repeated by the light emission discharge cells in which the wall charges remain, thereby the light emitting state is sustained (sustaining discharge stage).
A drive control circuit
50
is provided shown in FIG.
1
. Based on the timing of a supplied video signal, the drive control circuit
50
generates various switching signals for generating various driving pulses as shown in FIG.
2
. The generated switching signals are supplied to the column electrode driving circuit
20
and the row electrode driving circuits
30
and
40
.
The column electrode driving circuit
20
and the row electrode driving circuits
30
and
40
generate various driving pulses shown in
FIGS. 2A
to
2
F in accordance with the switching signals supplied from the drive control circuit
50
.
FIG. 3
is a diagram showing a driving pulse generating circuit which is provided in the row electrode driving circuit
30
and generates the reset pulse RP
y
and sustaining pulse IP
y
.
As
FIG. 3
shows, the driving pulse generating circuit has a capacitor C
1
whose one end is connected to a PDP grounding potential V
s
as a grounding potential of the PDP
10
. The driving pulse generating circuit also includes a plurality of switching elements S
1
through S
4
which are arranged in the manner as shown in the figure.
The switching element S
1
is in an OFF state for a period in which a switching signal SW
1
of the logic level “0” is supplied from the drive control circuit
50
. When the logic level of the switching signal SW
1
is equal to “1”, the switching element S
1
is in a connection state and an electric potential generated at the other end of the capacitor C
1
is applied onto a line
2
via a coil L
1
and a diode D
1
. The capacitor C
1
, consequently, starts discharging and an electric potential generated by the discharge is applied onto the line
2
.
The switching element S
2
is in the OFF state for a period in which a switching signal SW
2
of the logic level “0” is supplied from the drive control circuit
50
. The switching element S
2
is in the connection state when the logic level of the switching signal SW
2
is equal to “1” and the potential on the line
2
is applied to the other end of the capacitor C
1
via a coil L
2
and a diode D
2
. That is, the capacitor C
1
is charged by the potential on the line
2
.
The switching element S
3
is in the OFF state for a period in which a switching signal SW
3
of the logic level “0” is supplied from the drive control circuit
50
. When the logic level of the switching signal SW
3
is equal to “1”, the switching element S
3
is in the connecting state and a positive side terminal potential V
c
of a DC power source B
1
is applied onto the line
2
. The PDP grounding potential V
s
is applied to a negative side terminal of the DC power source B
1
.
The switching element S
4
is in the OFF state for a period in which a switching signal SW
4
of the logic level “0” is supplied from the drive control circuit
50
. When the logic level of the switching signal SW
4
is equal to “1”, the switching element S
4
is in the connection state and the PDP grounding potential V
s
is applied onto the line
2
.
The line
2
is connected to the row electrodes Y in the PDP
10
that has a load capacitance C
0
. In the row electrode driving circuit
30
, the circuits as shown in
FIG. 3
are provided for n systems that correspond to the number of row electrodes Y
1
to Y
n
.
FIGS. 4A
to
4
G are diagrams showing timings of the switching signals SW
1
to SW
4
which are supplied to the row electrode driving circuit
30
shown in
FIG. 3
from the drive control circuit
50
so as to generate the sustaining pulse IP
y
as shown in
FIGS. 2C
to
2
F onto the line
2
.
As shown in
FIGS. 4A
to
4
D, only the switching signal SW
4
among the switching signal
Lao Lun-Yi
Pioneer Electronic Corporation
Sughrue & Mion, PLLC
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