Computer graphics processing and selective visual display system – Display driving control circuitry – Display power source
Reexamination Certificate
2000-03-01
2002-11-12
Chang, Kent (Department: 2673)
Computer graphics processing and selective visual display system
Display driving control circuitry
Display power source
C345S060000
Reexamination Certificate
active
06480189
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a driving apparatus for an AC drive type plasma display panel (hereinafter called “PDP”) or a display panel having capacitive loads such as electroluminescence (hereinafter called “EL”) elements.
2. Description of the Related Background Art
Display apparatuses which use flat panels display devices of a self-emitting type such as a PDP or EL panel, are manufactured as on-wall TV's.
FIG. 1
is a diagram showing a schematic structure of the display apparatus.
In
FIG. 1
, a PDP
10
has row electrodes Y
1
to Y
n
and row electrodes X
1
to X
n
, each pair of which corresponds to a single one of rows of one screen (the first row to the n-th row). Further formed on the PDP
10
are column electrodes Z
1
to Z
m
which correspond to the respective columns of one screen (the first column to the m-th column) with an unillustrated dielectric layer and discharge space provided in between and which run perpendicular to those row electrode pairs. A single discharge cell C(i,j) is formed at each intersection of one pair of row electrodes (X, Y) and a single column electrode Z.
A row electrode driver
30
first generates reset pulses RP
Y
of a positive voltage as shown in FIG.
2
and simultaneously applies those pulses to the row electrodes Y
1
-Y
n
. At the same time, a row electrode driver
40
generates reset pulses RP
x
of a negative voltage and simultaneously applies those pulses to the row electrodes X
1
-X
n
.
The simultaneous application of those reset pulses RP
x
and RP
y
causes all the discharge cells of the PDP
10
to be excited and discharged, generating charge particles, and a predetermined amount of wall charges are evenly formed in the dielectric layers of the entire discharge cells after the discharging is finished (reset cycle).
After the reset cycle, a column electrode driver
20
generates pixel data pulses DP
1
to DP
n
respectively corresponding to the first row to the n-th row of the screen and sequentially applies the pixel data pulses to the column electrodes Z
1
-Z
m
as shown in FIG.
2
. In accordance with the application timing of the pixel data pulses DP
1
-DP
n
, the row electrode driver
30
generates a scan pulse SP of a negative voltage and sequentially applies the scan pulse SP to the row electrodes Y
1
-Y
n
, as shown in FIG.
2
.
In any discharge cells in the row electrode to which the scan pulse SP has been applied, discharging occurs and most of the wall charges are lost. Those discharge cells are cells to which the pixel data pulses of a positive voltage have also been applied at the same time. Since no discharging occurs in those discharge cells which have been applied with the scan pulse SP but not the pixel data pulses of a positive voltage, the wall charges remain. The discharge cells in which the wall charges have stayed become light-emitting discharge cells while those from which the wall charges have been lost become non-emitting discharge cells (address cycle).
When the address cycle ends, the row electrode drivers
30
and
40
continuously apply sustain pulses IP
y
of a positive voltage to the row electrodes Y
1
-Y
n
and continuously apply sustain pulses IP
x
of a positive voltage to the row electrodes X
1
-X
n
at timings different from the application timings of the sustain pulses IP
y
.
The light-emitting discharge cells where the wall charges have remained repeat discharge emission and maintain the light emission over a period in which the sustain pulses IP
x
and IP
y
are alternately applied (sustain discharge cycle).
A drive control circuit
50
shown in
FIG. 1
generates various switching signals for generating various drive pulses as shown in
FIG. 2
based on the timing of supplied video signals and supplies the switching signals to the column electrode driver
20
and the row electrode drivers
30
and
40
.
The column electrode driver
20
and the row electrode drivers
30
and
40
generate the various drive pulses shown in
FIG. 2
according to the switching signals supplied from the drive control circuit
50
.
FIG. 3
is a diagram illustrating a drive pulse generator which is provided in the row electrode driver
30
and generates the reset pulse RP
y
and the sustain pulse IP
y
.
In
FIG. 3
, the drive pulse generator is provided with a capacitor C
1
having one end grounded to a PDP ground potential V
s
as the ground potential of the PDP
10
.
A switching element S
1
is open when a switching signal SW
1
having a logic level “0” is being supplied from the drive control circuit
50
. When the logic level of the switching signal SW
1
is “1”, however, the switching element S
1
is closed, thereby applying the potential produced on the other end of the capacitor C
1
to a line
2
via a coil L
1
and a diode D
1
. As a result, the capacitor C
1
starts discharging and the potential generated by the discharge is applied to the line
2
.
A switching element S
2
is open when a switching signal SW
2
having a logic level “0” is being supplied from the drive control circuit
50
. When the logic level of the switching signal SW
2
is “1”, on the other hand, the switching element S
2
is closed, thereby applying the potential on the line
2
to the other end of the capacitor C
1
via a coil L
2
and a diode D
2
. That is, the capacitor C
1
is charged with the potential on the line
2
.
A switching element S
3
is open when a switching signal SW
3
of a logic level “0” is being supplied from the drive control circuit
50
. When the logic level of the switching signal SW
3
is “1”, however, the switching element S
3
is closed, thereby applying a positive terminal potential V
c
of a DC power supply B
1
to the line
2
. The negative terminal of the DC power supply B
1
is applied with the PDP ground potential V
s
.
A switching element S
4
is open when a switching signal SW
4
of a logic level “0” is being supplied from the drive control circuit
50
. When the logic level of the switching signal SW
4
is “1”, the switching element S
4
is closed, thereby applying the PDP ground potential V
s
to the line
2
.
The line
2
is connected to the row electrodes Y of the PDP
10
which has a capacitive element CO. That is, n circuits each as shown in
FIG. 3
corresponding to the row electrodes Y
1
-Y
n
are provided in the row electrode driver
30
.
FIG. 4
is a diagram showing timing of the switching signals SW
1
-SW
4
which the drive control circuit
50
supplies to the row electrode driver
30
shown in
FIG. 3
in order to produce the sustain pulse IP
y
shown in
FIG. 2
on the line
2
.
As shown in
FIG. 4
, since only the switching signal SW
4
of the switching signals SW
1
-SW
4
has a logic level “1” first, the switching element S
4
is closed to apply the PDP ground potential V
s
to the line
2
. During the period, the potential on the line
2
is the PDP ground potential Vs, i.e., 0 V.
When the logic levels of the switching signals SW
4
and SW
1
are respectively switched to “0” and “1”, only the switching element S
1
is closed, causing the charges stored in the capacitor C
1
to be discharged. Consequently, the current transiently flows across the coil L
1
with a waveform as illustrated in FIG.
4
. The current flows into the PDP
10
through the diode D
1
, the switching element S
1
and the line
2
, so that the capacitive element C
0
is charged. The potential on the line
2
gradually increases as shown in FIG.
4
.
When the logic levels of the switching signals SW
1
and SW
3
are respectively switched to “0” and “1”, only the switching element S
3
is closed, so that the positive terminal potential V
c
of a DC power supply B
1
is applied to the line
2
. Consequently, the potential on the line
2
is fixed to V
c
as shown in FIG.
4
.
When the logic levels of the switching signals SW
2
and SW
3
are respectively switched to “1” and “0”, only the switching element S
2
is closed, so that a negative current transiently flows across the coil L
2
with a waveform as illustrated in FIG.
4
. That is, the capaciti
Chang Kent
Pioneer Corporation
Sheng Tom V
Sughrue & Mion, PLLC
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