Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-02-03
2004-04-27
Liang, Regina (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S067000
Reexamination Certificate
active
06727869
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a matrix type display panel, such as lasma display panel, i.e. PDP, plasma addressed liquid crystal display, i.e. PALC, liquid crystal display, i.e. LCD, and their driving methods.
Display panels have been getting popular as a display means to replace CRTs, cathode ray tubes. PDPs in particular have been employed to public displays such as information board at rail road stations and air port terminals due to the advantageous features in the wide view angles and suitability to the wide display screen. Moreover, PDPs have become widely accepted in home use, such as television receivers and computer monitors, upon the practical success of the color screen.
2. Description of the Related Arts
In the display panels of matrix display type, a line sequential addressing operation, that is a setting operation of the contents to be displayed, was performed by the use of scan electrodes to designate cells, that is display elements, on each line and data electrodes to designate cells on each row.
A single scan electrode was arranged for each line; and a single data electrode was arranged for each row orthogonal to the lines in the prior art simple matrix type display panel. That is, in a screen having m rows and n lines as shown in
FIG. 14
, m data electrodes D
1
, D
2
. . . Dm and the n scan electrodes S
1
, S
2
. . . Sn were provided. The arrangement pitch of scan electrodes S
1
, S
2
. . . Sn was equal to the cell pitch along the row direction; and the arrangement pitch of data electrodes D
1
, D
2
. . . Dm was equal to the cell pitch along the line direction. In PDPs of three-electrode surface discharge type structure now commercially available as a color display device, two electrodes are arranged for each line;
however, this structure to define the individual cells can be considered as a simple matrix structure similar to that shown in
FIG. 14
because only one of the two electrodes is used for selecting the line.
In the prior art structures, there have been problems in that static capacitance between the electrodes becomes large.
Particularly in the color display panel including the cells of primary colors, R, G & B, aligning along the line direction, the influence of static capacitance between the data electrodes were serious because the row pitch is approximately one third of the line pitch. The cell size reduction to attempt the high resolution display causes an increase in the capacitance resulting in an increase in reactive power consumed in charging the capacitance. Waveforms of the driving pulses become less steep resulting in a considerable delay of the display response.
SUMMARY OF THE INVENTION
It is a general object of the invention to provide display panels and driving methods in which reactive power in the driving circuit is reduced by reducing electrostatic capacitance between the data electrodes.
In the present invention, two adjacent rows are grouped by a single data electrode an arrangement pitch of which is substantially twice the cell pitch along the line direction. Shape and dimension of the data electrode are chosen such that a single data electrode is related to both the adjacent rows. In order to enable selection of an individual cell on a single one of the grouped rows by designating the one of two rows, two or more scan electrodes are arranged for a single line. The shape of the data electrode is such as to effectively confront the scan electrodes at each cell of the related two rows.
Compared with the prior art structure in which a single data electrode is provided for each row, the space d between the adjacent two data electrodes is a value p−w, where the cell pitch p is reduced from the electrode width w; in the present invention, the data electrode space d is a value reducing the electrode width w from the double of the cell pitch
2
p, that is p−w.
In the displaying, a period allocated for a single line in a line sequential addressing period is divided so that the first and the second rows of each data electrode are set by time-sharing. Then, the number of the scan becomes twice the prior art method; however, when the screen is divided into two along the row direction it is possible to avoid the increase in the time required for the addressing of the whole screen by performing the addressing operation in parallel for the divided screens.
REFERENCES:
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patent: 4554537 (1985-11-01), Dick
patent: 5066890 (1991-11-01), Salavin et al.
patent: 5086257 (1992-02-01), Gay et al.
patent: RE33882 (1992-04-01), Morozumi
patent: 5182489 (1993-01-01), Sano
patent: 5825128 (1998-10-01), Betsui et al.
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patent: 0 800 157 (1997-10-01), None
patent: 2 061 612 (1981-05-01), None
patent: 8-179726 (1996-07-01), None
patent: 8-306318 (1996-11-01), None
Kehoe, J.L.: “Competitively Priced AC Plasma Displays”, Wescon Technical Papers, vol. 33,, Nov. 1, 1989, pp. 757-759.
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