Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Patent
1997-05-30
1999-04-27
Hjerpe, Richard A.
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
345 89, 345148, 348792, 348793, G09G 320
Patent
active
058984143
ABSTRACT:
A display apparatus permitting high resolution and a large number of gray-scale levels and causing indiscernible flicker has been disclosed. One frame is divided into or composed of j subframes, and light is produced according to a luminance level predetermined subframe by subframe in order to express intermediate gray-scale of a picture. Emphasis is put on the fact that display to be performed during each subframe within one frame can be controlled independently. An interlaced-scanning display is carried out during k subframes associated with low-order weighted bits out of j subframes, and a noninterlaced-scanning display is carried out during the other j-k subframes associated with high-order weighted bits. The ratio of an addressing scan time to a subframe associated with a small weight is large, and the ratio of an addressing scan time to a whole frame is very large. If the addressing scan time can be reduced as mentioned above, a great effect would be exerted. Moreover, the luminance levels to be determined in relation to the subframes during which interlaced-scanning display is carried out are so low that the influence of the reduction on a whole picture is limited.
REFERENCES:
patent: 5436634 (1995-07-01), Kanazawa
patent: 5475448 (1995-12-01), Saegusa
patent: 5583527 (1996-12-01), Fujisaki et al.
patent: 5701135 (1997-12-01), Aratani et al.
Asami Fumitaka
Awamoto Kenji
Hirose Tadatsugu
Matsui Naoki
Fujitsu Limited
Hjerpe Richard A.
Nguyen Francis N.
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