Display list processor for operating in processor and coprocesso

Details Display list processor for operating in processor and coprocesso Display list processor for operating in processor and coprocesso

1994-11-14

1998-01-06

Harrell, Robert B.

G09G 500

Patent

active

057064784

ABSTRACT:
A processor for executing display list command packets in processor or coprocessor mode of execution. The processor dynamically switches between the two modes based on the commands or interrupts received. Each display list packet includes a plurality of commands associated with a particular function, where each command includes a field for identifying the number of parameters associated with the command, if any. The parameters immediately follow the instruction in the instruction stream in a sequential format, eliminating address dependency. Each command preferably conforms to the same format regardless of location and mode of execution, so that the software and driver is simplified by not having to generate different code for different locations and modes. Thus, a host CPU executing an application program decides whether certain commands and command packets reside in system memory or within a local memory associated with the processor. The host CPU feeds commands to the processor in a coprocessor mode or sends an instruction commanding the processor to switch to processor mode and begin locating and executing commands. An idle instruction within the instruction stream places the processor back into coprocessor mode. In a graphics subsystem implemented according to the present invention, for example, a graphics processor executes display list packets associated with real-time graphics functions loaded into a private memory. Other, less time dependent commands may be fed by the host CPU or a DMA device to the graphics processor operating in coprocessor mode.

REFERENCES:
patent: 5388841 (1995-02-01), San et al.
Texas Instruments TMS34010 User's Guide, 1988, pp. 1-1-4-17.

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