Display FIFO memory management system

Details Display FIFO memory management system Display FIFO memory management system

1997-06-30

1999-09-14

Tung, Kee M.

Computer graphics processing and selective visual display system

Computer graphic processing system

Integrated circuit

345501, 345507, G09G 500

Patent

active

059530200

ABSTRACT:
A display FIFO memory management system and method includes a programmable FIFO emulator for emulating a drain and fill time of the display FIFO memory to automatically predict a number of register entries remaining in the display FIFO memory at each predefined clock cycle. A programmable timer/counter has programmable precision to accommodate varying bandwidths of display screen display modes and is used to determine the number of entries remaining so that the emulator can accommodate varying screen display modes. A FIFO controller controls the timing of fetching display data from memory to fill the display FIFO memory based on the prediction of the number of remaining register entries in the display FIFO by the programmable emulator.

REFERENCES:
patent: 5506809 (1996-04-01), Csoppenszky et al.
patent: 5617118 (1997-04-01), Thompson
patent: 5717440 (1998-02-01), Katsura et al.
patent: 5767866 (1998-06-01), Chee et al.
patent: 5804986 (1998-09-01), Jones

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