Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2000-01-05
2002-09-24
Lao, Lun-Yi (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S089000, C345S094000, C345S211000, C345S204000, C713S320000
Reexamination Certificate
active
06456271
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a display element driving device which is formed by cascade-connecting a plurality of driving circuits that drive a display element, such as a liquid crystal display element, based upon picture data signals, and concerns a display module using such a display element driving device.
BACKGROUND OF THE INVENTION
FIG. 12
shows a system construction on the source side of a conventional display element driving device used in a liquid crystal display element. Here, the number of pixels of a liquid crystal panel serving as the liquid crystal display element is
800
pixels×3 (RGB) [source side]×600 pixels [gate side].
In the above-mentioned display element driving device, each of source drivers LSI (Large Scale Integrated Circuit)
101
serving as a plurality of driving circuits on the source side carries out a displaying operation with 64 gradations, and drives 100 pixels×3 (RGB). Therefore, the display element driving device on the source side is constituted by 8 source drivers LSI
101
.
In the case when the eight source drivers LSI
101
have to be mutually distinguished, the source drivers LSI
101
at the respective 1 to 7 stages are referred to as the first to the seventh source drivers, and the source driver LSI
101
at the last stage is referred to as the eighth source driver.
Each source driver LSI
101
is packaged on a TCP (Tape Carrier Package) (not shown) and used. Here, in general, the TCP refers to a thin package made by bonding a driver LSI onto a film tape.
The above-mentioned display element driving device is provided with a controller
102
. Respective voltages outputted from the respective output terminals, VLS, Vcc, GND and Vrefs
1
to
9
, of the controller
102
are commonly supplied to the first to the eighth source drivers in parallel with each other. Moreover, various signals outputted from the respective output terminals, LS, R·G·B, SCK, of the controller
102
are also commonly supplied to the first to the eighth source drivers in parallel with each other. Here, a source driver starting pulse signal, outputted from an output terminal SSPI which will be described later, is successively transferred through the first to the eighth source drivers.
The following description will discuss flowing paths of the various signals released from the output terminals LS, R·G·B, SCK, SSPI of the controller
102
.
First, signal conductors of picture data signals R·G·B (R, G, B, each having 6 bits) outputted from the output terminals R·G·B of the controller
102
, a clock signal CK outputted from the output terminal SCK of the controller
102
and a latch signal LS outputted from the output terminal LS of the controller
102
are inputted to the first to the eighth source drivers in parallel with each other through respective common wires, Here, the source driver starting pulse signal SPI, outputted from the output terminal SSPI of the above-mentioned controller
102
, is inputted to the input terminal SPin of the first source driver. The source driver starting pulse signal SPI thus inputted is transferred through the first source driver, and outputted from the output terminal SPout as a source driver starting pulse signal SPO. The source driver starting pulse signal SPO outputted from the first source driver is inputted to the input terminal SPin of the second source driver at the next stage as the source driver starting pulse signal SPI. Thereafter, in the same manner, the source driver starting pulse signal SPI is transferred up to the eighth source driver while being shifted.
Moreover, voltages, such as a power supply voltage Vcc for use in the source driver LSI
101
, outputted from the output terminal Vcc of the controller
102
, a ground connection electric potential GND electrically connected to the output terminal GND of the controller
102
, 64 bit gradation displaying voltages Vrefs
1
to
9
outputted from the output terminals Vrefs
1
to
9
of the controller
102
, a liquid crystal panel applying voltage adjustment voltage VLS outputted from the output terminal VLS of the controller
102
, are supplied to the first to the eighth source drivers in parallel with each other through the respective common wires in the same manner as the above-mentioned flowing paths of the respective signals. Here, the power supply voltage Vcc, the ground connection electric potential GND, the 64 bit gradation displaying voltages Vrefs
1
to
9
, and the liquid crystal panel applying voltage adjustment voltage VLS are, hereinafter, referred to as power-supply-related voltages.
Next, referring to a block diagram of
FIG. 13
, an explanation will be given of the circuit construction of the source driver LSI
101
shown in FIG.
12
and of the operations of the first to eighth source drivers, while also referring to timing charts of the various signals shown in FIG.
14
.
As illustrated in
FIG. 13
, the source driver LSI
101
is constituted by a shift register
111
, a data latch circuit
112
, a sampling memory
113
, a hold memory
114
, a standard voltage generation circuit
115
, a D/A converter
116
and an output circuit
117
.
To the shift register
111
is inputted the source driver starting pulse signal SPI (see
FIG. 14
) outputted from the output terminal SSPI of the controller
102
through the input terminal SPin. The source driver starting pulse signal SPI is a signal synchronizing to the horizontal synchronizing signal of picture data signals R·G·B which will be described later. To the above-mentioned shift register
111
is inputted the clock signal CK (see
FIG. 14
) outputted from the output terminal SCK of the controller
102
through the first to the eighth source driver input terminals CKin.
By using the,source driver starting pulse signal SPI as a start pulse, the shift register
111
of the first source driver shifts the source driver starting pulse signal SPI in response to the first rise of the clock signal CK which has been inputted during the high level period of the source driver starting pulse signal SPI. The source driver starting pulse signal SPI, thus shifted, is outputted from the output terminal SPout of the first source driver as a source driver starting pulse signal SPO, and this is inputted to the input terminal SPin of the second source driver at the next stage. Thus, the source driver starting pulse signal SPI is shifted up to the eighth source driver at the final stage in the same manner.
Here, the picture data signals R·G·B, outputted from the output terminals R·G·B of the controller
102
consist of 6 bits respectively (see FIG.
14
). As illustrated in
FIG. 13
, these picture data signals R·G·B are inputted to the data latch circuit
112
in parallel with each other from the input terminals R
1
to
6
in, G
1
to
6
in, B
1
to
6
in. After having been temporarily latched in the data latch circuit
112
, the picture data signals R·G·B are supplied to the sampling memory
113
. The above-mentioned picture data signals R·G·B are color digital picture signals consisting of R(Red), G(Green), B(Blue), each having 6 bits (total 18 bits).
The above-mentioned sampling memory
113
samples the picture data signals R·G·B that are sent through the output signals from the respective stages of the shift register
111
in a time divided manner, and stores them until a latch signal LS (outputted from the output terminal LS of the controller
102
), which will be described later, is inputted.
Next, these picture data signals R·G·B are inputted to the hold memory
114
. At the time when data corresponding to one level period of the picture data signals R·G·B has been inputted to the hold memory
114
, they are latched by the latch signal LS inputted from the input terminal LSin. Up to the time when picture data signals R·G·B of the next level period have been inputted from the sampling memory
113
to the hold memory
114
, the hold memory
114
holds the data of one level period of the picture data signals R·G·B, and then outputs this to the D/A converter
Tamai Shigeki
Watanabe Toshio
Lao Lun-Yi
Sharp Kabushiki Kaisha
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