Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2000-04-10
2002-10-01
Mengistu, Amare (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S100000
Reexamination Certificate
active
06459417
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a driving device for driving an image display element, and particularly relates to a connection mode and signal supply mode of a liquid crystal driver to be mounted as a source driver or gate driver on a liquid crystal module.
BACKGROUND OF THE INVENTION
The following will describe a system structure of a display driving device of a conventional liquid crystal module referring to FIG.
14
.
As shown in
FIG. 14
, as a driving device for driving source bus lines of a liquid crystal panel
100
, there are provided n source drivers S (will be referred to as “group of source drivers S” hereinafter where appropriate) which are realized by source driver LSIs (Large Scale Integrated Circuits) each having a bidirectional shift register. The source drivers S are mounted on a liquid crystal panel
100
by being mounted on their corresponding TCP (Tape Carrier Package)
101
. The source drivers S are serially connected to one another to supply various signals such as start pulse signal SPD and clock signal CK, which are to be described later.
Each TCP
101
mounting a source driver S is electrically connected to the input terminal (not shown) of the liquid crystal panel
100
by its output terminal for the liquid crystal panel
100
, and the input terminal of the TCP is electrically connected to the wiring provided on a print substrate
102
, by which the liquid crystal panel
100
and print substrate
102
are electrically connected to each other via the group of source drivers S.
Controller
104
is connected to the print substrate
102
on the side of the source driver S(
1
). The controller
104
is for supplying control signals and power to the group of source drivers S, and the control signals and power are supplied to each source driver S via wiring on the print substrate
102
and wiring on TCP
101
. Note that, although not shown, the controller
104
also supplies control signals and power to a group of gate drivers.
The control signals and power supplied from the controller
104
include: start pulse signal SPD which is in synchronism with a horizontal synchronize signal of a video signal; clock signal CK; video signal Video; switch signal RL for deciding a transfer direction of the start pulse signal SPD in the source drivers S by switching a bidirectional shift register and input/output buffers of each source driver S, and power VCC and GND, etc.
In the structure of
FIG. 14
, the clock signal CK, video signal Video, switch signal RL, power VCC and GND supplied from the controller
104
are inputted to the first source driver S(
1
) via input terminal CK
1
, input terminal Video
1
, input terminal RL
1
, power terminal VCC, and power terminal GND, respectively. By transferring through inner wiring made of, for example, aluminium in the source driver S(
1
), these signals are then outputted from the source driver S(
1
) via output terminal CK
2
, output terminal Video
2
, output terminal RL
2
, output terminal VCC, and output terminal GND, respectively, to be inputted in the same manner to the source driver S(
2
) of the next stage.
Note that, the supply lines of the signals supplied from the controller
104
may be provided as a common line by the wiring on the print substrate
102
so that the signals are individually inputted to each source driver S.
Meanwhile, as shown in
FIG. 14
, there are provided two lines for the start pulse signal SPD, one entering the input/output terminal SPD
1
of the first source driver S(
1
), and one entering the input/output terminal SPD
2
of the nth source driver S(n), and input is made by selecting one of the lines. By selecting the input/output terminal SPD
1
or input/output terminal SPD
2
to which the start pulse signal SPD is to be inputted, the transfer direction of the start pulse signal SPD within the group of source drivers S is switched either from the source driver S(
1
) to the source driver S(n), or from the source driver S(n) to the source driver S(
1
). This selection of line for inputting the start pulse signal SPD is carried out by the controller
104
.
On the start pulse signal output stage of the controller
104
, there are provided switches SW
1
and SW
2
such as analog switches which are switched under the control of control signal SPA (/SPA is an inverted signal of SPA), and selection of line for outputting the start pulse signal SPD is realized by the switching control of the switches SW
1
and SW
2
.
When inputting through input/output terminal SPD
1
, the control signal SPA is set at “High” level. When the control signal SPA is at “High” level, the switch SW
1
on the side of SPD
1
is closed, and the switch SW
2
on the side of SPD
2
is opened. On the other hand, when inputting through input/output terminal SPD
2
, the control signal SPA is set at “Low” level. When the control signal SPA is at “Low” level, the switch SW
1
on the side of SPD
1
is opened, and the switch SW
2
on the side of SPD
2
is closed.
When the control signal SPA is at “High” level, the start pulse signal SPD is inputted from the input/output terminal SPD
1
of the source driver S(
1
) in synchronism with the clock signal CK, and by transferring through the bidirectional shift register in the source driver S(
1
), the signal is inputted into the source driver S(
2
) of the next stage and transferred subsequently to the source driver S(n) of the last stage through the serially connected source drivers S. Here, even though the start pulse signal SPD is outputted from the input/output terminal SPD
2
of the source driver S(n) of the last stage, because input is made from SPD
1
and the switch SW
2
of the controller
104
is open, the start pulse signal SPD is not transferred to the controller
104
.
On the other hand, when the control signal SPA is set at “Low” level, the start pulse signal SPD is inputted to the input/output terminal SPD
2
of the nth source driver S(n), which in this case is on the first stage, and the signal is transferred to the first source driver S(
1
), which in this case is on the last stage. As with the above case, even though the start pulse signal SPD is outputted from the input/output terminal SPD
1
of the source driver S(
1
) of the last stage, because input is made from SPD
2
and the switch SW
1
of the controller
104
is open, the signal is not transferred to the controller
104
. Further, in this case, the level of switch signal RL for deciding the transfer direction of the start pulse signal SPD in each source driver S is also set inversely.
The following will describe the system structure of
FIG. 14
in more detail referring to the block diagram of FIGS.
15
(
a
) and
15
(
b
). In FIGS.
15
(
a
) and
15
(
b
), OS
1
to OSm are output terminals to the liquid crystal panel
100
from each source driver S.
In FIG.
15
(
a
), the control signal SPA of the switches SW
1
and SW
2
in the controller
104
is at “High” level and the switch SW
1
on the side of SPD
1
is closed. In this state, the start pulse signal SPD is inputted to the input/output terminal SPD
1
of the source driver S(
1
) and it is outputted from the input/output terminal SPD
2
to be inputted to the input/output terminal SPD
1
of the source driver S(
2
) on the next stage, and the signal is transferred subsequently in the same manner.
In FIG.
15
(
b
), the level of control signal SPA of the switches SW
1
and SW
2
and the level of switch signal RL are set inversely, and the transfer direction of the start pulse signal SPD is reversed. That is, in FIG.
15
(
b
), the start pulse signal SPD is inputted from the input/output terminal SPD
2
of the nth source driver S(n) and is outputted from the input/output terminal SPD
1
to be inputted to the source driver S(n−1) of the next stage, and the signal is subsequently transferred to the first source driver S(
1
) in the same manner.
FIGS.
16
(
a
) and
16
(
b
) show an example in which the line connected to the input/output terminal SPD
1
of the source driver S(n) is directly connected to the controller
104
via wiring o
Ogawa Yoshinori
Orisaka Yukihisa
Mengistu Amare
Sharp Kabushiki Kaisha
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