Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-05-10
2001-06-12
Chang, Kent (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S100000, C345S182000, C345S519000
Reexamination Certificate
active
06246388
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a display driving circuit or displaying a predetermined character on a display panel.
2. Description of the Related Art
FIG. 8
is a block diagram showing a conventional display driving circuit formed integrated on a single chip.
The drawing includes an interface circuit
1
for receiving from an external device (such as a microcomputer) an operation enable signal CE, a clock signal CL, and various data DI for writing.
FIG. 9
shows a specific example of an interface circuit
1
. In the drawing, an address register
2
holds address data (e.g., eight bits) in synchronism with a clock signal CL when a chip enable signal CE is at an L level (low level), the address data serving as the key to the operation of the circuit shown in FIG.
8
. An address decoder
3
determines whether or not the value of the address register
2
is normal, and outputs “H” (high-level) when the value is determined to be normal. Upon completion of the determination by the address decoder
3
, an operation enable signal CE is changed from L to H level. An operation enable signal CE is supplied to one of the input terminals of an AND gate
4
, and also to another input terminal thereof via a delay circuit
5
and an inverter
6
. That is, when the operation enable signal CE rises from L to H level, the AND gate
4
outputs an H pulse signal. Meanwhile, an operation enable signal CE is also supplied to one of the input terminals of an OR gate
7
and as well as to another input terminal thereof via the delay circuit
5
and the inverter
6
. That is, when the operation enable signal CE falls from H to L level, the OR gate
7
outputs an L pulse signal. A D-type flip flop
8
is connected via the D terminal thereof to an output terminal of the address decoder
3
, via the C terminal thereof to an output terminal of the AND gate
4
, and via the R terminal thereof to an inverted signal of an output from the OR gate
7
. Thus, when an operation enable signal CE changes from L to H level, the D-type flip flop
8
holds an H output from the address decoder
3
, so that AND gates
9
and
10
are caused to be in an open state. Then, the AND gate
9
outputs various data DI (hereinafter referred to as SDI) for writing into a subsequent memory, and the AND gate
10
outputs a clock signal CL (hereinafter referred to as SCL). An output from the interface circuit
1
is supplied to a shift register (e.g., 24 bits) such that various data SDI is supplied to the shift register in synchronism with a clock signal SCL. When all bits of the various data SDI have been supplied to the shift register, an operation enable signal CE changes from H to L level, and the D-type flip flop
8
is reset. Accordingly, the AND gates
9
and
10
are caused to be in a closed state, thereby suspending shift operation of the shift register.
Referring again to
FIG. 8
, a shift register
11
, corresponding to the above mentioned shift register, serially receives various data SDI for a write of data into the memory (24 bits; D0 to D23) in synchronism with a clock signal SCL during a period when an operation enable signal CE remains at an H level. The shift register
11
is constituted as 24 D-type flip-flops connected in a cascade manner, and employs a serial input and a parallel output format. Note that various data SDI includes address data, display data, an instruction code, and so on.
A character generator ROM
12
stores character data (e.g., 5×7 dots (horizontal×vertical)) concerning a character to be displayed on a display panel (not shown). Note that the character generator ROM
12
is a non-volatile memory, such as a mask ROM, and is pre-stored, during manufacturing, with character data that is less likely to change. A character generator RAM
13
stores character data concerning other characters to be displayed on the display panel, similar to the character generator ROM
12
. Note that the character generator RAM
13
is a volatile memory, such as an SRAM, and stores character data that are very likely to change depending on the situation, under control of an external device. A display RAM
14
stores a character code for designating an address in the character generator ROM
12
or the character generator RAM
13
, with an address defined corresponding to each column of a display panel. For example, in the case of a display panel having 64 columns, when the address in the display RAM
14
corresponding to the first column of the display panel is 00H (H: hexadecimal), the address which corresponds to the 64th column is 3FH resulting from incremental addition. An accessory RAM
15
stores accessory data indicative of information other than characters to be displayed on the display panel with an address defined corresponding to each column of a display panel. For example, in the case of 16 types of available accessory information, when the address in the accessory RAM
15
corresponding to the first column of a display panel is OH, the address which corresponds to the 16th column is FH resulting from incremental addition. Note that the accessory RAM
15
is a volatile memory, such as an SRAM, similar to the character generator RAM
13
, and the accessory data stored therein can be rewritten as required.
An address counter
16
for use in reading a character code and accessory data supplies address data DCRDA0 to DCRDA5, each being six bits, to the display RAM
14
, and address data ADRDA0 to ADRDA3, each being four bits, to the accessory RAM
15
.
An instruction decoder
17
generates an instruction signal WCCK for writing character data into the character generator RAM
13
, an instruction signal WDCK for writing a character code into the display RAM
14
, and an instruction signal WACK for writing accessory data into the accessory RAM
15
.
FIG. 10
shows a specific example of an instruction decoder
17
. A decoder
18
selectively generates any one of the signals WCENB, WDENB, and WAENB according to the result of decoding the instruction code D20 to D23 supplied from the shift register
11
, the signals WCENB, WDENB, and WAENB being used as a base in preparing instruction signals WCCK, WDCK, and WACK. An output DIENB from the D-type flip flop
8
in the interface circuit
1
is supplied to one of the input terminals of a NOR gate
19
, and also to another input terminal thereof via a delay circuit
20
and an inverter
21
. That is, when a signal DIENB changes from H to L level after completion of shift operation using 24 bits by the shift register
11
, the NOR gate
19
outputs an H pulse signal. An output from the NOR gate
19
is supplied to one of the input terminals of each of the AND gates
22
,
23
, and
24
, while the signals WDENB, WAENB, and WCENB from the decoder
18
are supplied to other input terminals of the AND gates
22
,
23
, and
24
, respectively. That is, instruction signals WDCK, WACK, and WCCK are output from the AND gates
22
,
23
, and
24
, respectively, only during a period when an output from the NOR gate
19
remains at an H level.
FIG. 11
shows a specific example of a display RAM
14
. A volatile cell array
25
has a read enable terminal OE, a write enable terminal WE, address terminals A0 to A5, and data input/output terminals IO0 to IO7. Switching circuits
26
-
0
to
26
-
5
each comprise two AND gates and one OR gate. One of the two AND gates of each of the switching circuits
26
-
0
to
26
-
5
, i.e., the one shown above in each pair in the drawing, receives via one input terminal thereof corresponding read address data DCRDA0 to DCRDA 5, and receives via another input terminal thereof a switching signal DCRWCT. The AND gate shown below in each pair in the drawing receives via one input terminal thereof corresponding write address data D8 to D13 from the shift register
11
, and receives via another input terminal thereof an inverted signal of a switching signal DCRWCT. Latch circuits
27
-
0
to
27
-
5
each receive via an L terminal thereof an output from the OR gate of the correspondi
Arai Hiroyuki
Motegi Syuji
Tokunaga Tetsuya
Chang Kent
Hogan & Hartson LLP
Sanyo Electric Co,. Ltd.
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