Computer graphics processing and selective visual display system – Plural display systems – Diverse systems
Reexamination Certificate
2000-07-19
2002-10-29
Chang, Kent (Department: 2673)
Computer graphics processing and selective visual display system
Plural display systems
Diverse systems
C307S071000, C345S204000
Reexamination Certificate
active
06473059
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a display driver IC (integrated circuit) using a serial interface and also relates to an electronic device using the display driver IC.
2. Description of Related Art
Recent high integration of a single chip micro-controller has enabled many peripheral ICs to be controlled by the single chip micro-controller. An unrestricted increase in the number of the terminals of the single chip micro-controller is not permitted for reasons peculiar to each peripheral IC and hence there is a physical restriction on the number of terminals permitted within the range of the chip size. For these reasons, serial transmission is made between the single chip micro-controller and the peripheral ICs to thereby reduce the number of mutual terminals.
As a serial transmission system of this type, an I
2
C bus is known. This I
2
C (Inter-Integrated Circuits) bus includes only two bus lines, namely, a bidirectional serial data line (SDA) and a serial clock line (SCL) with the intention of establishing effective mutual control between ICs.
FIG. 6
shows the original I
2
C bus protocol. One byte information following a start condition bit S consists of a slave address and a read/write designation bit. A slave address is a specific address for identifying a plurality of slave ICs connected to a bus of a single chip micro-controller which is a master.
Command data, display data and the like are transmitted in byte units subsequent to the one byte information including a slave address, as shown in FIG.
6
. Each byte must be followed by an acknowledge bit A from a slave.
In
FIG. 6
, this one byte information which follows the one byte information including the slave address consists of a continuation bit C of one byte and command data of 7 bits. If the continuation bit C=0, this means that the data of 7 bits following the bit C is final command data, and if C=1, this means that other command data will further continue in one byte units. Then if necessary, display data is sent in byte unit after the final command data, and finally a stop condition bit P which is sent after an acknowledge bit terminates the transmission.
In the I
2
C bus protocol shown in
FIG. 6
, only 7 bits can be used for the command data since 1 bit in 1 byte is used as a continuation bit C. A technique in which a high order bit in data of one byte is used for another function in the above manner is also disclosed in Japanese Patent Application Laid-Open No. 7-13913. In this patent application, high order two bits in 1-byte serial data have a function of controlling the state of peripheral circuits, for example.
The I
2
C bus protocol shown in FIG.
7
and
FIG. 8
is developed to make it possible to send command data of one byte or more.
Subsequent to the one byte information including a slave address and to an acknowledge bit A, two bytes information including a control byte and command data is sent, as shown in FIG.
7
. Command bits of low order 8 bits in the latter command data and the remainder of the high order command bits in the former control byte enable to output command data comprising data of one byte (8 bits) and more. It is to be noted that the highest order bit C
0
of the control byte functions as the continuation bit.
In
FIG. 8
, a D/C bit is provided as a second high order bit of a control byte to determine which of a command or data follows.
The I
2
C bus protocol comprises, as the multi-master-bus, all formats and procedures in a system, enabling specifications for controlling the bus by a plurality of micro-controllers as masters, for example, and hence it has high application flexibility. However, since many requirements must be fulfilled to control specific ICs, it is not always convenient to use the I
2
C bus protocol.
Meanwhile, the serial transmission system has the advantage that the number of terminals can be reduced to a greater extent than that of a parallel transmission system. However, this serial transmission system is inferior in speed of data transmission. In the actual situation, for example, an increase in the size of a liquid crystal screen cause liquid crystal display drivers or the like to be faced with demands for high speed data transmission.
However, the outlined I
2
C bus protocol is limited in the speed-up of data transmission. This is because one byte including a slave address is required to be located at the top of each byte of a command and data, and an acknowledge bit A sent from a slave IC is always required subsequent to individual one byte information. Because the information transmitted between the master and the slave is increased in this manner, speed-up of data transmission is limited. Moreover, presence of the acknowledge bit A decreases the transfer rate of serial clock signals and restricts the speed-up of data transmission because of the following reasons.
FIG. 9
shows a signal line L of a serial data line SDA. A source voltage VCC is applied to the signal line L via a pull-up resistance R
1
and the signal line L has its own wiring capacitance C. A switch SW consisting of a MOS transistor is disposed on the side of a slave IC. This switch SW is turned on to discharge the charge of the signal line L
1
to thereby drop the potential to 0 V, supplying the aforementioned acknowledge bit A from the slave IC to a master micro-controller. A resistance R
3
shown in
FIG. 9
is a total resistance (such as an ITO wiring resistance and a connector resistance) from a terminal of the IC to a substrate. At this time, since the switch SW has an on-resistance R
2
, a time depending on the time constant decided by the resistance R
1
, R
2
, and R
3
and the wiring capacitance C, is required for discharging the signal line L
1
. It is therefore necessary to determine the frequency of the serial clock signal on the basis of the time constant. This frequency is 100 kHz in a standard mode, about 400 kHz in a fast mode, and about 3.4 MHz even in a high-speed mode.
In a semiconductor-manufacturing process used to realize a high performance micro-controller, progress is being made in miniaturization. Source voltage is decreased to a lower voltage level corresponding to the miniaturization in the process.
With the decrease in source voltage, the on-resistance R
2
of the switch SW formed by a MOS transistor for sending the acknowledge bit A of the slave IC is increased. The time constant for discharging the signal line L
1
is thereby increased. This also hinders the speed-up of data transmission.
Moreover, the pull-up resistance R
1
and the resistance (R
2
+R
3
) divide the voltage to create a 0 level for the acknowledge bit A. The larger the resistance (R
2
+R
3
), the higher the potential at the 0 level and the smaller an allowable noise margin.
SUMMARY OF THE INVENTION
In view of the above situation, it is an objective of the present invention to provide a display driver IC which adopts a serial transmission system to reduce the number of terminal pins, transmits a command and data efficiently, and also can deal with the speed-up of data transmission and a reduction in the voltage of interface signals, and to provide an electronic device using the display driver IC.
According to a first aspect of the present invention, there is provided a display driver IC comprising:
an interface circuit to which signals from an external MPU are input;
a command decoder for decoding command data input from the external MPU through the interface circuit;
a storage section in which display data input from the external MPU through the interface is written; and
a display driving section for driving a display on the basis of the display data written in the storage section,
wherein the interface circuit comprises:
a first input terminal to which one unit data column of (N+1) bits is input serially, the one unit data column including data groups of N bits which are simultaneously processed by the external MPU and identification data of one bit which identifies whether the data groups are groups of the
Chang Kent
Oliff & Berridg,e PLC
Seiko Epson Corporation
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