Display driver and display unit and electronic apparatus...

Computer graphics processing and selective visual display system – Display driving control circuitry

Reexamination Certificate

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C345S088000, C345S097000, C345S098000, C345S100000, C345S092000, C345S095000, C345S099000, C345S205000, C345S204000, C345S208000, C345S211000, C345S213000, C365S154000, C365S156000, C365S185130, C365S185010, C365S185230, C365S189011, C365S230010, C365S230060, C365S220000, C365S221000, C369S053130, C369S053130, C369S059160, C369S060010, C369S176000, C369S242000

Reexamination Certificate

active

06724378

ABSTRACT:

Japanese patent application No. 2001-41762, filed on Feb. 19, 2001 hereby incorporated by reference in its entirety.
TECHNICAL FIELD
The present invention relates to a display driver and a display unit and an electronic apparatus utilizing the same.
BACKGROUND
In display sections of portable electronic apparatus such as portable telephones and Personal Digital Assistants (PDAs), liquid crystal panels are often used which preferably realize reduced sizes, weights, and power consumption. A display section constituted by such a liquid crystal panel or the like is driven for display by a display driver.
To display a still-image or moving-image, a display driver outputs still-image data or moving-image data to a display section in a constant period. Therefore, power consumption is reduced by incorporating a RAM for storing such data in the display driver. For the purpose of further reducing the size, weight, and power consumption of such a display driver, it is considered effective to improve the level of integration by using a miniaturization process.
SUMMARY
One aspect of the invention relates to a display driver incorporating a RAIVI formed of at least a plurality of memory cells provided for each pixel. Each of the memory cells includes a flip-flop having first and second nodes which store logic levels complementary to each other; a first switching element which electrically connects a first bit line with the first node when a first word line becomes active; and a second switching element which electrically connects a second bit line with the first node when a second word line becomes active. Each of the memory cells further includes a setting circuit which sets the second node at a first logic level based on a set signal and a circuit which outputs the logic level stored at the second node to a display read line based on a given read signal. The display driver includes a set signal generation circuit which generates the set signal for each pixel. The set signal sets the second node at the first logic level for the memory cells for a pixel.


REFERENCES:
patent: 5717638 (1998-02-01), Kim
patent: 5812148 (1998-09-01), Takasugi et al.
patent: 6025822 (2000-02-01), Motegi et al.

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